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APRIL 2005
XRT75L06D
REV. 1.0.4
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
GENERAL DESCRIPTION
The XRT75L06D is a six channel fully integrated Line Interface Unit (LIU) for E3/DS3/STS-1 applications. The LIU incorporates 6 independent Receivers, Transmitters and Jitter Attenuators in a single 217 Lead BGA package. Each channel of the XRT75L06D can be independently configured to operate in E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz). Each transmitter can be turned off and tri-stated for redundancy support or for conserving power. The XRT75L06D's differential receiver provides high noise interference margin and is able to receive data over 1000 feet of cable or with up to 12 dB of cable attenuation. The XRT75L06D incorporates an advanced crystalless jitter attenuator per channel that can be selected either in the transmit or receive path. The jitter attenuator performance meets the ETSI TBR-24 and Bellcore GR-499 specifications. Also, the jitter FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L06D
attenuators can be used for clock smoothing in SONET STS-1 to DS-3 de-mapping. The XRT75L06D provides a Parallel Microprocessor Interface for programming and control. The XRT75L06D supports analog, remote and digital loop-backs. The device also has a built-in Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error for diagnostic purposes.
APPLICATIONS * E3/DS3 Access Equipment * DSLAMs * Digital Cross Connect Systems * CSU/DSU Equipment * Routers * Fiber Optic Terminals
CS RD WR Addr[7:0] D[7:0] PCLK RDY INT Pmode RESET
XRT75L06D XRT75L06D
Processor Interface
CLKOUT_n SFM_en RLOL_n E3Clk DS3Clk STS-Clk/12M
MUX
Peak Detector Slicer Clock & Data Recovery LOS Detector
Clock Synthesizer Jitter Attenuator HDB3/ B3ZS Decoder
RTIP_n RRing_n
AGC/ Equalizer
RxClk_n RxPOS_n RxNEG/LCV_n
Local LoopBack
Remote LoopBack RLOS_n TxClk_n TxPOS_n TxNEG_n
TTIP_n TRing_n MTIP_n MRing_n DMO_n ICT
Line Driver
Tx Pulse Shaping
Timing Control
Jitter Attenuator
MUX
HDB3/ B3ZS Encoder
Device Monitor
Tx Control
TxON Channel 0 Channel n... Channel 5
ORDERING INFORMATION
PART NUMBER XRT75L06DIB PACKAGE 217 Lead BGA OPERATING TEMPERATURE RANGE -40C to +85C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT75L06D
REV. 1.0.4
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FEATURES
RECEIVER
* On chip Clock and Data Recovery circuit for high
input jitter tolerance
* 5 V Tolerant digital inputs * Available in 217 pin BGA Package * - 40C to 85C Industrial Temperature Range
TRANSMIT INTERFACE CHARACTERISTICS
* Meets E3/DS3/STS-1 Jitter Tolerance Requirement * Detects and Clears LOS as per G.775 * Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
* Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal to the line
* On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
* Integrated Pulse Shaping Circuit * Built-in B3ZS/HDB3 Encoder (which can be
disabled)
* On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
* Accepts Transmit Clock with duty cycle of 30%70%
* Provides low jitter output clock
TRANSMITTER
* Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications
* Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
* Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE and ANSI T1.102_1993
* Tri-state Transmit output capability for redundancy
applications
* Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253CORE
* Each Transmitter can be turned on or off
JITTER ATTENUATOR
* On chip advanced crystal-less Jitter Attenuator for
each channel
* Transmitter can be turned off in order to support
redundancy designs RECEIVE INTERFACE CHARACTERISTICS
* Jitter Attenuator can be selected in Receive,
Transmit path, or disabled
* Integrated Adaptive Receive Equalization (optional)
for optimal Clock and Data Recovery
* Meets ETSI TBR 24 Jitter Transfer Requirements * Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995 standards
* Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications
* Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
* 16 or 32 bits selectable FIFO size
CONTROL AND DIAGNOSTICS
* Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
* Parallel Microprocessor Interface for control and
configuration
* Supports
monitoring
* Declares Loss of Lock (LOL) Alarm * Built-in B3ZS/HDB3 Decoder (which can be
disabled)
optional
internal
Transmit
driver
* Each channel supports Analog, Remote and Digital
Loop-backs
* Recovered Data can be muted while the LOS
Condition is declared
* Single 3.3 V 5% power supply
* Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FIGURE 2. XRT75L06D IN BGA PACKAGE (BOTTOM VIEW)
XRT75L06D
REV. 1.0.4
(See pin list for pin names and function)
A B C D E F G H J K L
XRT75L06D
M N P R T U
17
16
15
14
12
12
11
10
9
8
7
6
5
4
3
2
1
3
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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REV. 1.0.4
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................ 1
APPLICATIONS............................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L06D............................................................................................................................ 1
ORDERING INFORMATION.................................................................................................................... 1 FEATURES .................................................................................................................................................... 2 TRANSMIT INTERFACE CHARACTERISTICS....................................................................................................... 2 RECEIVE INTERFACE CHARACTERISTICS......................................................................................................... 2
FIGURE 2. XRT75L06D IN BGA PACKAGE (BOTTOM VIEW) .............................................................................................................. 3
TABLE OF CONTENTS...................................................................................................... I PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
TRANSMIT INTERFACE.................................................................................................................................... 4 RECEIVE INTERFACE...................................................................................................................................... 6 CLOCK INTERFACE ........................................................................................................................................ 8 CONTROL AND ALARM INTERFACE ....................................................................................................... 9 ANALOG POWER AND GROUND .................................................................................................................... 12 DIGITAL POWER AND GROUND ..................................................................................................................... 14 1.0 CLOCK SYNTHESIZER ......................................................................................................................... 16
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR ...................................... 16
1.1 CLOCK DISTRIBUTION .................................................................................................................................... 16
FIGURE 4. CLOCK DISTRIBUTION CONGIFURED IN E3 MODE WITHOUT USING SFM.......................................................................... 16
2.0 THE RECEIVER SECTION .................................................................................................................... 17
FIGURE 5. RECEIVE PATH BLOCK DIAGRAM .................................................................................................................................... 17
2.1 RECEIVE LINE INTERFACE ............................................................................................................................. 17
FIGURE 6. RECEIVE LINE INTERFACECONNECTION .......................................................................................................................... 17
2.2 ADAPTIVE GAIN CONTROL (AGC) ................................................................................................................. 18 2.3 RECEIVE EQUALIZER ...................................................................................................................................... 18
FIGURE 7. ACG/EQUALIZER BLCOK DIAGRAM................................................................................................................................. 18 2.3.1 RECOMMENDATIONS FOR EQUALIZER SETTINGS ................................................................................................ 18
2.4 CLOCK AND DATA RECOVERY ...................................................................................................................... 18
2.4.1 DATA/CLOCK RECOVERY MODE .............................................................................................................................. 18 2.4.2 TRAINING MODE.......................................................................................................................................................... 18
2.5 LOS (LOSS OF SIGNAL) DETECTOR.............................................................................................................. 19
2.5.1 DS3/STS-1 LOS CONDITION ....................................................................................................................................... 19 TABLE 1: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ............................................................................................................................................ 19 2.5.2 DISABLING ALOS/DLOS DETECTION ....................................................................................................................... 19 2.5.3 E3 LOS CONDITION:.................................................................................................................................................... 20 FIGURE 8. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775............................................................................................ 20 FIGURE 9. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ........................................................................................... 20 2.5.4 INTERFERENCE TOLERANCE.................................................................................................................................... 21 FIGURE 10. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 21 FIGURE 11. INTERFERENCE MARGIN TEST SET UP FOR E3.............................................................................................................. 21 TABLE 2: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 22 2.5.5 MUTING THE RECOVERED DATA WITH LOS CONDITION: ..................................................................................... 23 FIGURE 12. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING ................................................................................................. 23
2.6 B3ZS/HDB3 DECODER..................................................................................................................................... 23
3.0 THE TRANSMITTER SECTION ............................................................................................................. 24
FIGURE 13. TRANSMIT PATH BLOCK DIAGRAM ................................................................................................................................ 24
3.1 TRANSMIT DIGITAL INPUT INTERFACE ........................................................................................................ 24
FIGURE 14. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75L06D (DUAL-RAIL DATA) ...................................... 24 FIGURE 15. TRANSMITTER TERMINAL INPUT TIMING ........................................................................................................................ 25 FIGURE 16. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)............................................................ 25
3.2 TRANSMIT CLOCK ........................................................................................................................................... 26 3.3 B3ZS/HDB3 ENCODER..................................................................................................................................... 26
3.3.1 B3ZS ENCODING ......................................................................................................................................................... FIGURE 18. B3ZS ENCODING FORMAT ........................................................................................................................................... 3.3.2 HDB3 ENCODING......................................................................................................................................................... FIGURE 17. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED) ............................................................................. FIGURE 19. HDB3 ENCODING FORMAT .......................................................................................................................................... 26 26 26 26 27
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
3.4 TRANSMIT PULSE SHAPER ............................................................................................................................ 27
FIGURE 20. TRANSMIT PULSE SHAPE TEST CIRCUIT ....................................................................................................................... 27 3.4.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................... 27
3.5 E3 LINE SIDE PARAMETERS .......................................................................................................................... 28
FIGURE 21. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703....................................................................... 28 TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ....................................................... 29 FIGURE 22. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS .......................... 30 TABLE 4: STS-1 PULSE MASK EQUATIONS ..................................................................................................................................... 30 TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) .............................. 31 FIGURE 23. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ................................................................... 31 TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 32 TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 32
3.6 TRANSMIT DRIVE MONITOR ........................................................................................................................... 33
FIGURE 24. TRANSMIT DRIVER MONITOR SET-UP. ........................................................................................................................... 33
3.7 TRANSMITTER SECTION ON/OFF .................................................................................................................. 33
4.0 JITTER ................................................................................................................................................... 34
4.1 JITTER TOLERANCE........................................................................................................................................ 34
FIGURE 25. JITTER TOLERANCE MEASUREMENTS ........................................................................................................................... 34 4.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS .................................................................................................. 34 FIGURE 26. INPUT JITTER TOLERANCE FOR DS3/STS-1................................................................................................................ 35 4.1.2 E3 JITTER TOLERANCE REQUIREMENTS................................................................................................................ 35 FIGURE 27. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 35 TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) .................................................................... 36
4.2 JITTER TRANSFER........................................................................................................................................... 36
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES .............................................................................................................. 36
4.3 JITTER ATTENUATOR ..................................................................................................................................... 36
TABLE 10: JITTER TRANSFER PASS MASKS .................................................................................................................................... 37 FIGURE 28. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 37 4.3.1 JITTER GENERATION.................................................................................................................................................. 37
5.0 DIAGNOSTIC FEATURES..................................................................................................................... 38
5.1 PRBS GENERATOR AND DETECTOR ............................................................................................................ 38
FIGURE 29. PRBS MODE ............................................................................................................................................................. 38
5.2 LOOPBACKS .................................................................................................................................................... 39
5.2.1 ANALOG LOOPBACK.................................................................................................................................................. FIGURE 30. ANALOG LOOPBACK..................................................................................................................................................... 5.2.2 DIGITAL LOOPBACK ................................................................................................................................................... FIGURE 31. DIGITAL LOOPBACK...................................................................................................................................................... 5.2.3 REMOTE LOOPBACK .................................................................................................................................................. FIGURE 32. REMOTE LOOPBACK .................................................................................................................................................... 39 39 40 40 40 40
5.3 TRANSMIT ALL ONES (TAOS) ........................................................................................................................ 41
FIGURE 33. TRANSMIT ALL ONES (TAOS)...................................................................................................................................... 41
6.0 MICROPROCESSOR INTERFACE BLOCK ......................................................................................... 42
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ................................................................................................... 42 FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK.................................................................. 42
6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ............................................................................ 43
TABLE 12: XRT75L06D MICROPROCESSOR INTERFACE SIGNALS ................................................................................................... 43
6.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION............................................................................. 44
FIGURE 35. ASYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ........................... 45 TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS ...................................................................................................................... 45 FIGURE 36. SYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ............................. 46 TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS ........................................................................................................................ 46 FIGURE 37. INTERRUPT PROCESS................................................................................................................................................... 47 6.2.1 HARDWARE RESET: ................................................................................................................................................... 48 TABLE 15: REGISTER MAP AND BIT NAMES .................................................................................................................................... 48 TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ......................................................................................................................... 49 TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5) ................................................................... 49 TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N ................................................................................................................... 51
7.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ................................................................. 56
7.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS .............................. 56
FIGURE 38. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ........ 57
7.2 MAPPING/DE-MAPPING JITTER/WANDER .................................................................................................... 58
7.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................... 58 FIGURE 39. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME .............................................................................................. 59 FIGURE 40. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
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60 FIGURE 41. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME .......................................................................................... 61 FIGURE 42. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME .......................................................................................... 62 FIGURE 43. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE....................................................................................... 63 FIGURE 44. AN ILLUSTRATION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE... 64 FIGURE 45. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO AN STS-1 SPE ............................................................................................................................................................. 64 7.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ........................................... 65 FIGURE 46. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE .............................. 66 FIGURE 47. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL ............................................................... 67 FIGURE 48. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL ........................................................................... 69
7.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS.................................................................................. 69
7.3.1 THE CONCEPT OF AN STS-1 SPE POINTER............................................................................................................. 69 FIGURE 49. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES .................................... 70 FIGURE 50. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION OF THE J1 BYTE, DESIGNATED ........................................................................................................................................ 71 FIGURE 51. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2 BYTES) AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-1 FRAME ............................... 71 7.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK .................................................................................... 71 7.3.3 CAUSES OF POINTER ADJUSTMENTS ..................................................................................................................... 72 FIGURE 52. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER ............................................................. 73 FIGURE 53. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS DESIGNATED .................................................................................................................................................................. 74 FIGURE 54. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS DESIGNATED .................................................................................................................................................................. 75 7.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ................................................................................. 76
7.4 CLOCK GAPPING JITTER ................................................................................................................................ 76
FIGURE 55. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION.................................. 76
7.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR DS3 APPLICATIONS ...................................................................................................................................... 77
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3 APPLICATIONS .. 77 7.5.1 DS3 DE-MAPPING JITTER........................................................................................................................................... 78 7.5.2 SINGLE POINTER ADJUSTMENT ............................................................................................................................... 78 FIGURE 56. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO ......................................................................................... 78 7.5.3 POINTER BURST.......................................................................................................................................................... 78 FIGURE 57. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO ..................................................................................... 79 7.5.4 PHASE TRANSIENTS................................................................................................................................................... 79 FIGURE 58. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO ..................................................................... 79 7.5.5 87-3 PATTERN.............................................................................................................................................................. 80 FIGURE 59. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN ............................................................. 80 7.5.6 87-3 ADD ....................................................................................................................................................................... 80 FIGURE 60. ILLUSTRATION OF THE 87-3 ADD POINTER ADJUSTMENT PATTERN ................................................................................ 81 7.5.7 87-3 CANCEL................................................................................................................................................................ 81 FIGURE 61. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO................................................................................ 81 7.5.8 CONTINUOUS PATTERN............................................................................................................................................. 82 FIGURE 62. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO ................................................................ 82 7.5.9 CONTINUOUS ADD ..................................................................................................................................................... 82 FIGURE 63. ILLUSTRATION OF CONTINUOUS-ADD POINTER ADJUSTMENT SCENARIO......................................................................... 83 7.5.10 CONTINUOUS CANCEL............................................................................................................................................. 83 FIGURE 64. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO ................................................................... 83
7.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997...................................... 84 7.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM APPLICATION................................................................................................................................................. 84
7.7.1 INTRINSIC JITTER TEST RESULTS............................................................................................................................ 84 TABLE 20: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ..................................... 84 7.7.2 WANDER MEASUREMENT TEST RESULTS.............................................................................................................. 85
7.8 DESIGNING WITH THE LIU .............................................................................................................................. 85
7.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRINSIC JITTER AND WANDER REQUIREMENTS.................................................................................................................... 85 FIGURE 65. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS .......................... 85
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 .................................................... 86 CHANNEL 1 ADDRESS LOCATION = 0X0E ............................................ 86 CHANNEL 2 ADDRESS LOCATION = 0X16 ............................................ 86
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 87 87 87 87 87 87 88 88 88 88 88 88
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06.................................................... CHANNEL 1 ADDRESS LOCATION = 0X0E................................................. CHANNEL 2 ADDRESS LOCATION = 0X16 .................................................. JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07.................................. CHANNEL 1 ADDRESS LOCATION = 0X0F..................................... CHANNEL 2 ADDRESS LOCATION = 0X17 ..................................... JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07................................... CHANNEL 1 ADDRESS LOCATION = 0X0F............................... CHANNEL 2 ADDRESS LOCATION = 0X17 ............................... JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07................................... CHANNEL 1 ADDRESS LOCATION = 0X0F.............................. CHANNEL 2 ADDRESS LOCATION = 0X17 ..............................
7.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ........................ 88 FIGURE 66. ILLUSTRATION OF MINOR PATTERN P1 .................................................................................................................... 89 FIGURE 67. ILLUSTRATION OF MINOR PATTERN P2 .................................................................................................................... 90 FIGURE 68. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A .................................................. 90 FIGURE 69. ILLUSTRATION OF MINOR PATTERN P3 .................................................................................................................... 91 FIGURE 70. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B............................................................... 91 FIGURE 71. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC ............................... 92 FIGURE 72. SIMPLE ILLUSTRATION OF THE LIU BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION .................................... 92 7.8.3 HOW DOES THE LIU PERMIT THE USER TO COMPLY WITH THE SONET APS RECOVERY TIME REQUIREMENTS OF 50MS (PER TELCORDIA GR-253-CORE)? ............................................................................................................ 92 TABLE 21: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ......................................................................... 93
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07................................... 93 CHANNEL 1 ADDRESS LOCATION = 0X0F.............................. 93 CHANNEL 2 ADDRESS LOCATION = 0X17 .............................. 93
7.8.4 HOW SHOULD ONE CONFIGURE THE LIU, IF ONE NEEDS TO SUPPORT "DAISY-CHAIN" TESTING AT THE END CUSTOMER'S SITE?..................................................................................................................................................... 94
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07................................... CHANNEL 1 ADDRESS LOCATION = 0X0F..................................... CHANNEL 2 ADDRESS LOCATION = 0X17 ..................................... 8.0 ELECTRICAL CHARACTERISTICS .....................................................................................................
94 94 94 95
TABLE 22: ABSOLUTE MAXIMUM RATINGS ....................................................................................................................................... 95 TABLE 23: DC ELECTRICAL CHARACTERISTICS: .............................................................................................................................. 95
APPENDIX A ................................................................................................................... 96
TABLE 24: TRANSFORMER RECOMMENDATIONS .................................................................................................................. 96 TABLE 25: TRANSFORMER DETAILS ................................................................................................................................................ 96
ORDERING INFORMATION ................................................................................................................. 98 PACKAGE DIMENSIONS - 23 X 23 MM 217 LEAD BGA PACKAGE .................................................................. 98
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PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
LEAD # T15 R16 R15 N14 P14 P13 SIGNAL NAME TxON_0 TxON_1 TxON_2 TxON_3 TxON_4 TxON_5 TYPE I DESCRIPTION Transmitter ON Input - Channel 0: Transmitter ON Input - Channel 1: Transmitter ON Input - Channel 2: Transmitter ON Input - Channel 3: Transmitter ON Input - Channel 4: Transmitter ON Input - Channel 5: These pins are active only when the corresponding TxON bits are set. Table below shows the status of the transmitter based on theTxON bit and TxON pin settings.
Bit 0 0 1 1 Pin 0 1 0 1 Transmitter Status OFF OFF OFF ON
NOTES: 1. 2. 3. E3 M3 F15 P16 G3 H15 TxCLK_0 TxCLK_1 TxCLK_2 TxCLK_3 TxCLK_4 TxCLK_5 I These pins will be active and can control the TTIP and TRING outputs only when the TxON_n bits in the channel register are set . When Transmitters are turned off the TTIP and TRING outputs are Tristated. These pins are internally pulled up.
Transmit Clock Input for TPOS and TNEG - Channel 0: Transmit Clock Input for TPOS and TNEG - Channel 1: Transmit Clock Input for TPOS and TNEG - Channel 2: Transmit Clock Input for TPOS and TNEG - Channel 3: Transmit Clock Input for TPOS and TNEG - Channel 4: Transmit Clock Input for TPOS and TNEG - Channel 5: The frequency accuracy of this input clock must be of nominal bit rate 20 ppm. The duty cycle can be 30%-70%. By default, input data is sampled on the falling edge of TxCLK.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TRANSMIT INTERFACE
LEAD # F2 P2 G15 R17 H3 K15 SIGNAL NAME TNEG_0 TNEG_1 TNEG_2 TNEG_3 TNEG_4 TNEG_5 TYPE I DESCRIPTION Transmit Negative Data Input - Channel 0: Transmit Negative Data Input - Channel 1: Transmit Negative Data Input - Channel 2: Transmit Negative Data Input - Channel 3: Transmit Negative Data Input - Channel 4: Transmit Negative Data Input - Channel 5: In Dual-rail mode, these pins are sampled on the falling or rising edge of TxCLK_n . NOTES: 1. These input pins are ignored and must be grounded if the Transmitter Section is configured to accept Single-Rail data from the Terminal Equipment.
F3 N3 F16 P15 G2 J15
TPOS_0 TPOS_1 TPOS_2 TPOS_3 TPOS_4 TPOS_5
I
Transmit Positive Data Input - Channel 0: Transmit Positive Data Input - Channel 1: Transmit Positive Data Input - Channel 2: Transmit Positive Data Input - Channel 3: Transmit Positive Data Input - Channel 4: Transmit Positive Data Input - Channel 5: By default sampled on the falling edge of TxCLK.
D1 N1 D17 N17 H1 H17
TTIP_0 TTIP_1 TTIP_2 TTIP_3 TTIP_4 TTIP_5
O
Transmit TTIP Output - Channel 0: Transmit TTIP Output - Channel 1: Transmit TTIP Output - Channel 2: Transmit TTIP Output - Channel 3: Transmit TTIP Output - Channel 4: Transmit TTIP Output - Channel 5: These pins along with TRING transmit bipolar signals to the line using a 1:1 transformer.
E1 M1 E17 M17 J1 J17
TRING_0 TRING_1 TRING_2 TRING_3 TRING_4 TRING_5
O
Transmit Ring Output - Channel 0: Transmit Ring Output - Channel 1: Transmit Ring Output - Channel 2: Transmit Ring Output - Channel 3: Transmit Ring Output - Channel 4: Transmit Ring Output - Channel 5: These pins along with TTIP transmit bipolar signals to the line using a 1:1 transformer.
5
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER RECEIVE INTERFACE
LEAD # A2 U2 A17 U17 D8 P8 SIGNAL NAME RxCLK_0 RXCLK_1 RxCLK_2 RxCLK_3 RxCLK_4 RxCLK_5 TYPE O DESCRIPTION
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Receive Clock Output - Channel 0: Receive Clock Output - Channel 1: Receive Clock Output - Channel 2: Receive Clock Output - Channel 3: Receive Clock Output - Channel 4: Receive Clock Output - Channel 5: By default, RPOS and RNEG data sampled on the rising edge RxCLK.. Set the RxCLKINV bit to sample RPOS/RNEG data on the falling edge of RxCLK Receive Positive Data Output - Channel 0: Receive Positive Data Output - Channel 1: Receive Positive Data Output - Channel 2: Receive Positive Data Output - Channel 3: Receive Positive Data Output - Channel 4: Receive Positive Data Output - Channel 5: NOTE: If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are removed and replaced with `0'.
A1 U1 A16 U16 D9 P9
RPOS_0 RPOS_1 RPOS_2 RPOS_3 RPOS_4 RPOS_5
O
B2 T2 B16 T16 D10 P10
RNEG_0/ LCV_0 RNEG_1/ LCV_1 RNEG_2/ LCV_2 RNEG_3/ LCV_3 RNEG_4/ LCV_4 RNEG_5/ LCV_5 RRING_0 RRING_1 RRING_2 RRING_3 RRING_4 RRING_5
O
Receive Negative Data Output/Line Code Violation Indicator - Channel 0: Receive Negative Data Output/Line Code Violation Indicator - Channel 1: Receive Negative Data Output/Line Code Violation Indicator - Channel 2: Receive Negative Data Output/Line Code Violation Indicator - Channel 3: Receive Negative Data Output/Line Code Violation Indicator - Channel 4: Receive Negative Data Output/Line Code Violation Indicator - Channel 5: In Dual Rail mode, a negative pulse is output through RNEG. Line Code Violation Indicator - Channel n: If configured in Single Rail mode then Line Code Violation will be output.
A5 U5 A14 U14 A9 U9
I
Receive Input - Channel 0: Receive Input - Channel 1: Receive Input - Channel 2: Receive Input - Channel 3: Receive Input - Channel 4: Receive Input - Channel 5: These pins along with RTIP receive the bipolar line signal from the remote DS3/ E3/STS-1 Terminal.
6
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
RECEIVE INTERFACE
LEAD # A6 U6 A13 U13 A10 U10 SIGNAL NAME RTIP_0 RTIP_1 RTIP_2 RTIP_3 RTIP_4 RTIP_5 TYPE I Receive Input - Channel 0: Receive Input - Channel 1: Receive Input - Channel 2: Receive Input - Channel 3: Receive Input - Channel 4: Receive Input - Channel 5: These pins along with RRING receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal. DESCRIPTION
7
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER CLOCK INTERFACE
LEAD # E15 SIGNAL NAME E3CLK TYPE I DESCRIPTION E3 Clock Input (34.368 MHz 20 ppm):
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If any of the channels is configured in E3 mode, a reference clock 34.368 MHz is applied on this pin. NOTE: In single frequency mode, this reference clock is not required. G16 DS3CLK I DS3 Clock Input (44.736 MHz 20 ppm): If any of the channels is configured in DS3 mode, a reference clock 44.736 MHz. is applied on this pin. NOTE: In single frequency mode, this reference clock is not required. C16 STS-1CLK/ 12M I STS-1 Clock Input (51.84 MHz 20 ppm): If any of the channels is configured in STS-1 mode, a reference clock 51.84 MHz is applied on this pin.. In Single Frequency Mode, a reference clock of 12.288 MHz 20 ppm is connected to this pin and the internal clock synthesizer generates the appropriate clock frequencies based on the configuration of the channels in E3, DS3 or STS-1 modes. L15 SFM_EN I Single Frequency Mode Enable: Tie this pin "High" to enable the Single Frequency Mode. A reference clock of 12.288 MHz 20 ppm is applied. In the Single Frequency Mode (SFM) a low jitter output clock is provided for each channel if the CLK_EN bit is set thus eliminating the need for a separate clock source for the framer. Tie this pin "Low" if single frequency mode is not selected. In this case, the appropriate reference clocks must be provided. NOTE: B1 T1 B17 T17 D11 P11 CLKOUT_0 CLKOUT_1 CLKOUT_2 CLKOUT_3 CLKOUT_4 CLKOUT_5 O This pin is internally pulled down
Clock output for channel 0 Clock output for channel 1 Clock output for channel 2 Clock output for channel 3 Clock output for channel 4 Clock output for channel 5 Low jitter clock output for each channel based on the mode selection (E3,DS3 or STS-1) if the CLKOUTEN_n bit is set in the control register. This eliminates the need for a separate clock source for the framer. NOTES: 1. 2. The maximum drive capability for the clockouts is 16 mA. This clock out is available both in SFM and non-SFM modes.
8
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
CONTROL AND ALARM INTERFACE
LEAD # B7 R6 C14 R14 C6 D14 SIGNAL NAME MRING_0 MRING_1 MRING_2 MRING_3 MRING_4 MRING_5 TYP
E
DESCRIPTION Monitor Ring Input - Channel 0: Monitor Ring Input - Channel 1: Monitor Ring Input - Channel 2: Monitor Ring Input - Channel 3: Monitor Ring Input - Channel 4: Monitor Ring Input - Channel 5: The bipolar line output signal from TRING_n is connected to this pin via a 270 resistor to check for line driver failure. NOTE: This pin is internally pulled up.
I
B8 R7 C13 R13 C7 D13
MTIP_0 MTIP_1 MTIP_2 MTIP_3 MTIP_4 MTIP_5
I
Monitor Tip Input - Channel 0: Monitor Tip Input - Channel 1: Monitor Tip Input - Channel 2: Monitor Tip Input - Channel 3: Monitor Tip Input - Channel 4: Monitor Tip Input - Channel 5: The bipolar line output signal from TTIP_n is connected to this pin via a 270ohm resistor to check for line driver failure. NOTE: This pin is internally pulled up.
C5 T4 B12 T12 D5 B15
DMO_0 DMO_1 DMO_2 DMO_3 DMO_4 DMO_5
O
Drive Monitor Output - Channel 0: Drive Monitor Output - Channel 1: Drive Monitor Output - Channel 2: Drive Monitor Output - Channel 3: Drive Monitor Output - Channel 4: Drive Monitor Output - Channel 5: If MTIP_n and MRING_n has no transition pulse for 128 32 TxCLK_n cycles, DMO_n goes "High" to indicate the driver failure. DMO_n output stays "High" until the next AMI signal is detected.
C8 T7 C12 T11 B11 R8
RLOS_0 RLOS_1 RLOS_2 RLOS_3 RLOS_4 RLOS_5
O
Receive Loss of Signal - Channel 0: Receive Loss of Signal - Channel 1: Receive Loss of Signal - Channel 2: Receive Loss of Signal - Channel 3: Receive Loss of Signal - Channel 4: Receive Loss of Signal - Channel 5: This output pin toggles "High" if the receiver has detected a Loss of Signal Condition.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER CONTROL AND ALARM INTERFACE
C9 T8 D12 R11 C11 R9 RLOL_0 RLOL_1 RLOL_2 RLOL_3 RLOL_4 RLOL_5 O Receive Loss of Lock - Channel 0: Receive Loss of Lock - Channel 1: Receive Loss of Lock - Channel 2: Receive Loss of Lock - Channel 3: Receive Loss of Lock - Channel 4: Receive Loss of Lock - Channel 5:
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This output pin toggles "High" if a Loss of Lock Condition is detected. LOL (Loss of Lock) condition occurs if the recovered clock frequency deviates from the Reference Clock frequency (available at either E3CLK or DS3CLK or STS1CLK input pins) by more than 0.5%. L16 RXA **** External Resistor of 3.01K 1%. Should be connected between RxA and RxB for internal bias. External Resistor of 3.01K 1%. Should be connected between RxA and RxB for internal bias. In-Circuit Test Input: Setting this pin "Low" causes all digital and analog outputs to go into a highimpedance state to allow for in-circuit testing. For normal operation, tie this pin "High". NOTE: This pin is internally pulled up. R12 TEST **** Factory Test Pin NOTE: This pin must be connected to GND for normal operation.
K16
RXB
****
P12
ICT
I
MICROPROCESSOR INTERFACE
LEAD # K3 SIGNAL NAME CS TYPE I DESCRIPTION Chip Select Tie this "Low" to enable the communication with the Microprocessor Interface. Processor Clock Input To operate the Microprocessor Interface, appropriate clock frequency is provided through this pin. Maximum frequency is 66 Mhz. Write Data : To write data into the registers, this active low signal is asserted. Read Data: To read data from the registers, this active low pin is asserted. Register Reset: Setting this input pin "Low" resets the contents of the Command Registers to their default settings and default operating configuration NOTE: This pin is internally pulled up. L3 PMODE I Processor Mode Select: When this pin is tied "High", the microprocessor is operating in synchronous mode which means that clock must be applied to the PCLK (pin 55). Tie this pin "Low" to select the Asynchronous mode. An internal clock is provided for the microprocessor interface.
R1
PCLK
I
K2
WR
I
L2
RD
I
J3
RESET
I
10
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
MICROPROCESSOR INTERFACE
LEAD # T3 SIGNAL NAME RDY TYPE O Ready Acknowledge: NOTE: This pin must be connected to VDD via 3 k 1% resistor. U3 INT O INTERRUPT Output: A transition to "Low" indicates that an interrupt has been generated. The interrupt function can be disabled by clearing the interrupt enable bit in the Channel Control Register. NOTES: 1. This pin will remain asserted "Low" until the interrupt is serviced. 2. This pin must be conneced to VDD via 3 k 1% resistor. B4 A3 B3 C4 C3 C2 D3 D4 N4 P3 P4 P5 R5 R4 R3 R2 ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] I ADDRESS BUS: 8 bit address bus for the microprocessor interface DESCRIPTION
I/O
DATA BUS: 8 bit Data Bus for the microprocessor interface
11
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER ANALOG POWER AND GROUND
LEAD # E2 N2 E16 N16 J2 J16 D2 M2 D16 M16 H2 H16 A4 U4 A15 U15 A8 U8 A7 U7 A12 U12 A11 U11 E4 K4 E14 K14 G4 G14 F4 J4 SIGNAL NAME TxAVDD_0 TxAVDD_1 TxAVDD_2 TxAVDD_3 TxAVDD_4 TxAVDD_5 TxAGND_0 TxAGND_1 TxAGND_2 TxAGND_3 TxAGND_4 TxAGND_5 RxAVDD_0 RxAVDD_1 RxAVDD_2 RxAVDD_3 RxAVDD_4 RxAVDD_5 RxAGND_0 RxAGND_1 RxAGND_2 RxAGND_3 RxAGND_4 RxAGND_5 JaAVDD_0 JaAVDD_1 JaAVDD_2 JaAVDD_3 JaAVDD_4 JaAVDD_5 JaAGND_0 JaAGND_1 TYPE **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** DESCRIPTION Transmitter Analog 3.3 V 5% VDD - Channel 0 Transmitter Analog 3.3 V 5% VDD - Channel 1 Transmitter Analog 3.3 V 5% VDD - Channel 2 Transmitter Analog 3.3 V 5% VDD - Channel 3 Transmitter Analog 3.3 V 5% VDD - Channel 4 Transmitter Analog 3.3 V 5% VDD - Channel 5 Transmitter Analog GND - Channel 0 Transmitter Analog GND - Channel 1 Transmitter Analog GND - Channel 2 Transmitter Analog GND - Channel 3 Transmitter Analog GND - Channel 4 Transmitter Analog GND - Channel 5 Receiver Analog 3.3 V 5% VDD - Channel 0 Receiver Analog 3.3 V 5% VDD - Channel 1 Receiver Analog 3.3 V 5% VDD - Channel 2 Receiver Analog 3.3 V 5% VDD - Channel 3 Receiver Analog 3.3 V 5% VDD - Channel 4 Receiver Analog 3.3 V 5% VDD - Channel 5 Receiver Analog GND - Channel_0 Receive Analog GND - Channel 1 Receive Analog GND - Channel 2 Receive Analog GND - Channel 3 Receive Analog GND - Channel 4 Receive Analog GND - Channel 5 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 0 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 1 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 2 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 3 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 4 Analog 3.3 V 5% VDD - Jitter attenuator Channel 5 Analog GND - Jitter Attenuator Channel 0 Analog GND - Jitter Attenuator Channel 1
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12
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
ANALOG POWER AND GROUND
LEAD # F14 J14 H4 H14 C10 R10 H9 J9 K9 N15 M15 SIGNAL NAME JaAGND_2 JaAGND_3 JaAGND_4 JaAGND_5 AGND AGND AGND AGND AGND REFAVDD REFGND TYPE **** **** **** **** **** **** **** **** **** **** **** DESCRIPTION Analog GND - Jitter Attenuator Channel 2 Analog GND - Jitter Attenuator Channel 3 Analog GND - Jitter Attenuator Channel 4 Analog GND - Jitter Attenuator Channel 5 Analog GND Analog GND Analog GND Analog GND Analog GND Analog 3.3 V 5% VDD - Reference Reference GND
13
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER DIGITAL POWER AND GROUND
LEAD # F1 L1 F17 L17 K1 K17 C1 P1 C17 P17 G1 G17 B5 T5 B14 T14 B9 T9 B6 T6 B13 T13 B10 T10 P6 C15 L4 D6 L14 D15 D7 M14 SIGNAL NAME TxVDD_0 TxVDD_1 TxVDD_2 TxVDD_3 TxVDD_4 TxVDD_5 TxGND_0 TxGND_1 TxGND_2 TxGND_3 TxGND_4 TxGND_5 RxDVDD_0 RxDVDD_1 RxDVDD_2 RxDVDD_3 RxDVDD_4 RxDVDD_5 RxDGND_0 RxDGND_1 RxDGND_2 RxDGND_3 RxDGND_4 RxDGND_5 DVDD_1 DVDD_2 JaDVDD_1 DVDD(uP) JaDVDD_2 DGND_1 DGND(uP) JaDGND_2 TYPE **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** DESCRIPTION Transmitter 3.3 V 5% VDD Channel 0 Transmitter 3.3 V 5% VDD Channel 1 Transmitter 3.3 V 5% VDD Channel 2 Transmitter 3.3 V 5% VDD Channel 3 Transmitter 3.3 V 5% VDD Channel 4 Transmitter 3.3 V 5% VDD Channel 5 Transmitter GND - Channel 0 Transmitter GND - Channel 1 Transmitter GND - Channel 2 Transmitter GND - Channel 3 Transmitter GND - Channel 4 Transmitter GND - Channel 5 Receiver 3.3 V 5% VDD - Channel 0 Receiver 3.3 V 5% VDD - Channel 1 Receiver 3.3 V 5% VDD - Channel 2 Receiver 3.3 V 5% VDD - Channel 3 Receiver 3.3 V 5% VDD - Channel 4 Receiver 3.3 V 5% VDD - Channel 5 Receiver Digital GND - Channel 0 Receiver Digital GND - Channel 1 Receiver Digital GND - Channel 2 Receiver Digital GND - Channel 3 Receiver Digital GND - Channel 4 Receiver Digital GND - Channel 5 VDD 3.3 V 5% VDD 3.3 V 5% VDD 3.3 V 5% VDD 3.3 V 5% VDD 3.3 V 5% Digital GND Digital GND Digital GND
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14
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
DIGITAL POWER AND GROUND
LEAD # M4 P7 H8 J8 K8 H10 J10 K10 SIGNAL NAME JaDGND_1 DGND DGND DGND DGND DGND DGND DGND TYPE **** **** **** **** **** **** **** **** Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND DESCRIPTION
15
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
1.0 CLOCK SYNTHESIZER
The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks used to drive the LIU. The reference clock used to supply the microprocessor timing is generated from the DS3 or SFM clock input. Therefore, if the chip is configured for STS-1 only or E3 only, then the DS-3 input pin must be connected to the STS-1 pin or E3 pin respectively. In DS-3 mode or when SFM is used, the STS-1 and E3 input pins can be left unconnected. If SFM is enabled by pulling the SFM_EN pin "High", 12.288MHz is the only clock reference necessary to generate DS-3, E3, or STS-1 line rates and the microprocessor timing. A simplified block diagram of the clock synthesizer is shown in Figure 3
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR
SFM_EN STS-1Clk/12M DS3Clk E3Clk
Clock Synthesizer
CLKOUT_n LOL_n
0 1
Processor
1.1
Clock Distribution
Network cards that are designed to support multiple line rates which are not configured for single frequency mode should ensure that a clock is applied to the DS3Clk input pin. For example: If the network card being supplied to an ISP requires E3 only, the DS-3 input clock reference is still necessary to provide read and write access to the internal microprocessor. Therefore, the E3 mode requires two input clock references. If however, multiple line rates will not be supported, i.e. E3 only, then the DS3Clk input pin may be hard wire connected to the E3Clk input pin.
FIGURE 4. CLOCK DISTRIBUTION CONGIFURED IN E3 MODE WITHOUT USING SFM
DS3Clk
E3Clk
Clock Synthesizer
CLKOUT_n LOL_n
Processor
NOTE: For one input clock reference, the single frequency mode should be used.
16
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2.0 THE RECEIVER SECTION
The receiver is designed so that the LIU can recover clock and data from an attenuated line signal caused by cable loss or flat loss according to industry specifications. Once data is recovered, it is processed and presented at the receiver outputs according to the format chosen to interface with a Framer/Mapper or ASIC. This section describes the detailed operation of various blocks within the receive path. A simplified block diagram of the receive path is shown in Figure 5.
FIGURE 5. RECEIVE PATH BLOCK DIAGRAM
Peak Detector Slicer Clock & Data Recovery LOS Detector Channel n Jitter Attenuator HDB3/ B3ZS Decoder RxClk_n RxPOS_n RxNEG/LCV_n RLOS_n
RTIP_n RRing_n
AGC/ Equalizer
MUX
2.1
Receive Line Interface
Physical Layer devices are AC coupled to a line interface through a 1:1 transformer. The transformer provides isolation and a level shift by blocking the DC offset of the incoming data stream. The typical medium for the line interface is a 75 coxial cable. Whether using E3, DS-3 or STS-1, the LIU requires the same bill of materials, see Figure 6.
FIGURE 6. RECEIVE LINE INTERFACECONNECTION
1:1 RTIP_n Receiver 75 RRing_n
DS-3/E3/STS-1
37.5
37.5
0.01F RLOS_n
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 2.2 Adaptive Gain Control (AGC)
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The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The peak detector provides feedback to the equalizer before slicing occurs.
2.3 Receive Equalizer
The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to generate Positive and Negative data. The equalizer can be disabled by programming the appropriate register.
FIGURE 7. ACG/EQUALIZER BLCOK DIAGRAM
Peak Detector Slicer LOS Detector
RTIP_n RRing_n
AGC/ Equalizer
2.3.1
Recommendations for Equalizer Settings
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/ STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable, the Equalizer can be enabled. However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse template requirements), it is recommended that the Equalizer be disabled for cable length less than 300 feet. This would help to prevent over-equalization of the signal and thus optimize the performance in terms of better jitter transfer characteristics. The Equalizer also contains an additional 20 dB gain stage to provide the line monitoring capability of the resistively attenuated signals which may have 20dB flat loss. The equalizer gain mode can be enabled by programming the appropriate register.
NOTE: The results of extensive testing indicate that even when the Equalizer was enabled, regardless of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial Temperature.
2.4
Clock and Data Recovery
The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the following two modes:
2.4.1 Data/Clock Recovery Mode
In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on the RxClk_n out pins is the Recovered Clock signal.
2.4.2 Training Mode
In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of Lock condition is declared by toggling RLOL_n output pin "High" or setting the RLOL_n bit to "1" in the control register. Also, the clock output on the RxClk_n pins are the same as the reference channel clock.
18
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2.5 2.5.1
LOS (Loss of Signal) Detector DS3/STS-1 LOS Condition
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 75 consecutive zeros occur on the line. When the DLOS condition occurs, the DLOS_n bit is set to "1" in the status control register. DLOS condition is cleared when the detected average pulse density is greater than 33% for 175 75 pulses. Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the threshold as shown in the Table 1.The status of the ALOS condition is reflected in the ALOS_n status control register. RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled "High" and the RLOS_n bit is set to "1" in the status control register.
TABLE 1: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION REQEN SETTING LOSTHR SETTING DS3 0 1 0 1 STS-1 0 1 0 1 0 0 1 1 0 0 1 1 SIGNAL LEVEL TO DECLARE ALOS DEFECT < 75mVpk < 45mVpk < 120mVpk < 55mVpk < 120mVpk < 50mVpk < 125mVpk < 55mVpk SIGNAL LEVEL TO CLEAR ALOS DEFECT > 130mVpk > 60mVpk > 45mVpk > 180mVpk > 170mVpk > 75mVpk > 205mVpk > 90mVpk
2.5.2
Disabling ALOS/DLOS Detection
For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a "1" to both ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 2.5.3 E3 LOS Condition:
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If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the LOS condition is detected. Loss of signal is defined as no transitions for 10 to 255 consecutive zeros. No transitions is defined as a signal level between 15 and 35 dB below the normal. This is illustrated in Figure 8. The LOS condition is cleared within 10 to 255 UI after restoration of the incoming line signal. Figure 9 shows the LOS declaration and clearance conditions.
FIGURE 8. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB -15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
FIGURE 9. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.
Actual Occurrence of LOS Condition RTIP/ RRing Line Signal is Restored
10 UI
255 UI
Time Range for LOS Declaration
10 UI
255 UI
RLOS Output Pin 0 UI G.775 Compliance 0 UI Time Range for LOS Clearance G.775 Compliance
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2.5.4
Interference Tolerance
For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error free clock and data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same recommendation is being used. Figure 10 shows the configuration to test the interference margin for DS3/ STS1. Figure 11 shows the set up for E3.
FIGURE 10. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
Attenuator Sine Wave Generator N
DS3 = 22.368 MHz STS-1 = 25.92 MHz
Cable Simulator Pattern Generator 2 23 -1 PRBS S
DUT XRT75L06D
Test Equipment
FIGURE 11. INTERFERENCE MARGIN TEST SET UP FOR E3.
Attenuator 1 Sine Wave Generator 17.184mHz N Attenuator 2
Signal Source 223-1 PRBS Cable Simulator S
DUT XRT75L06D Test Equipment
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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TABLE 2: INTERFERENCE MARGIN TEST RESULTS
MODE CABLE LENGTH (ATTENUATION) INTERFERENCE TOLERANCE Equalizer "IN" E3 0 dB 12 dB 0 feet DS3 225 feet 450 feet 0 feet STS-1 225 feet 450 feet -17 dB -14 dB -15 dB -15 dB -14 dB -15 dB -14 dB -14 dB
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2.5.5
Muting the Recovered Data with LOS condition:
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to "1".
NOTE: When the LOS condition is cleared, the recovered data is output on RxPOS_n and RxNEG_n pins.
FIGURE 12. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING
tRRX RxClk tLCVO LCV tCO RPOS or RNEG
tFRX
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
RxClk
Duty Cycle RxClk Frequency E3 DS-3 STS-1
45
50
55
%
34.368 44.736 51.84 2 2 4 4 4 2.5
MHz MHz MHz ns ns ns ns
tRRX tFRX tCO tLCVO
RxClk rise time (10% o 90%) RxClk falling time (10% to 90%) RxClk to RPOS/RNEG delay time RxClk to rising edge of LCV output delay
2.6
B3ZS/HDB3 Decoder
The decoder block takes the output from the clock and data recovery block and decodes the B3ZS (for DS3 or STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data stream. Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active "High" pulse is generated on the RLCV_n output pins to indicate line code violation.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 3.0 THE TRANSMITTER SECTION
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The transmitter is designed so that the LIU can accept serial data from a local device, encode the data properly, and then output an analog pulse according to the pulse shape chosen in the appropriate registers. This section describes the detailed operation of various blocks within the transmit path. A simplified block diagram of the transmit path is shown in Figure 13.
FIGURE 13. TRANSMIT PATH BLOCK DIAGRAM
TTIP_n TRing_n MTIP_n MRing_n DMO_n
Line Driver
Tx Pulse Shaping
Timing Control
Jitter Attenuator
MUX
HDB3/ B3ZS Encoder
TxClk_n TxPOS_n TxNEG_n
Device Monitor
Tx Control Channel n
TxON
3.1
Transmit Digital Input Interface
The method for applying data to the transmit inputs of the LIU is a serial interface consisting of TxClk, TxPOS, and TxNEG. For single rail mode, only TxClk and TxPOS are necessary for providing the local data from a Framer device or ASIC. Data can be sampled on either edge of the input clock signal by programming the appropriate register. A typical interface is shown in Figure 14.
FIGURE 14. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75L06D (DUAL-RAIL DATA)
TxPOS Terminal Equipment (E3/DS3 or STS-1 Framer) TxNEG TxLineClk
TPData TNData TxClk
Transmit Logic Block
Exar E3/DS3/STS-1 LIU
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FIGURE 15. TRANSMITTER TERMINAL INPUT TIMING
tRTX TxClk tTSU tTHO tFTX
TPData or TNData TTIP or TRing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TxClk
Duty Cycle TxClk Frequency E3 DS-3 STS-1
30
50
70
%
34.368 44.736 51.84 4 4 3 3
MHz MHz MHz ns ns ns ns
tRTX tFTX tTSU tTHO
TxClk Rise Time (10% to 90%) TxClk Fall Time (10% to 90%) TPData/TNData to TxClk falling set up time TPData/TNData to TxClk falling hold time
FIGURE 16. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)
Data
1
1
0
TPData TxClk
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FIGURE 17. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED)
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Data
1
1
0
TPData TNData TxClk
3.2
Transmit Clock
The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736 MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle clock to the pulse shaping circuit. This allows a 30% to 70% duty cycle Transmit Clock to be supplied.
3.3 B3ZS/HDB3 ENCODER
When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS format (for either DS3 or STS-1) or HDB3 format (for E3).
3.3.1 B3ZS Encoding
An example of B3ZS encoding is shown in Figure 18. If the encoder detects an occurrence of three consecutive zeros in the data stream, it is replaced with either B0V or 00V, where `B' refers to Bipolar pulse that is compliant with the Alternating polarity requirement of the AMI (Alternate Mark Inversion) line code and `V' refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of B0V or 00V is made so that an odd number of bipolar pulses exist between any two consecutive violation (V) pulses. This avoids the introduction of a DC component into the line signal.
FIGURE 18. B3ZS ENCODING FORMAT
TClk TPDATA Line Signal
1 1 0 0 1 11 1 0 0 1 0 0 V 0 0 B 0 0 0 V B V 0 0 0
0 0
0 0
0 V
0 0
1
3.3.2
HDB3 Encoding
An example of the HDB3 encoding is shown in Figure 19. If the HDB3 encoder detects an occurrence of four consecutive zeros in the data stream, then the four zeros are substituted with either 000V or B00V pattern. The substitution code is made in such a way that an odd number of pulses exist between any consecutive V pulses. This avoids the introduction of DC component into the analog signal.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FIGURE 19. HDB3 ENCODING FORMAT
TClk TPDATA Line Signal
1 1 0 0 1 11 1 0 0 0 0 0 0 0 V 1 1 0 0 0 0 0 0 V 0 0 B 0 0 0 0 0 V
3.4
TRANSMIT PULSE SHAPER
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark Inversion (AMI) pulse that meets the industry standard mask template requirements for STS-1 and DS3. For E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped pulse with very little slope. The Pulse Shaper Block also includes a Transmit Build Out Circuit, which can either be disabled or enabled by setting the TxLEV_n bit to "1" or "0" in the control register. For DS3/STS-1 rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that transmit pulse template requirements are met at the Cross-Connect system. The distance between the transmitter output and the Cross-Connect system can be between 0 to 450 feet. For E3 rate, since the output pulse template is measured at the secondary of the transformer and since there is no Cross-Connect system pulse template requirements, the Transmit Build Out Circuit is always disabled. The differential line driver increases the transmit waveform to appropriate level and drives into the 75 load as shown in Figure 20.
FIGURE 20. TRANSMIT PULSE SHAPE TEST CIRCUIT
R1
TxPOS(n) TxNEG(n) TxLineClk(n)
TPData(n) TNData(n) TxClk(n) TRing(n)
TTIP(n)
31.6 +1%
R2
31.6 + 1%
R3 75 1:1
3.4.1
Guidelines for using Transmit Build Out Circuit
If the distance between the transmitter and the DSX3 or STSX-1, Cross-Connect system, is less than 225 feet, enable the Transmit Build Out Circuit by setting the TxLEV_n control bit to "0". If the distance between the transmitter and the DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit.
27
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 3.5 E3 line side parameters
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The XRT75L06D line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure 7.
FIGURE 21. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703
17 ns (14.55 + 2.45)
V = 100%
8.65 ns
Nominal Pulse
50%
14.55ns 12.1ns (14.55 - 2.45) 10% 20%
10% 0%
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (Measured at secondary of the transformer) Transmit Output Pulse Amplitude Ratio Transmit Output Pulse Width Transmit Intrinsic Jitter RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) Interference Margin Jitter Tolerance @ Jitter Frequency 800KHz Signal level to Declare Loss of Signal Signal Level to Clear Loss of Signal Occurence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time NOTE: The above values are at TA = 250C and VDD = 3.3 V 5%. -15 10 10 255 255 900 -20 0.15 1200 -14 0.28 -35 feet dB UIPP dB dB UI UI 0.95 12.5 1.00 14.55 0.02 1.05 16.5 0.05 ns UIPP 0.90 1.00 1.10 Vpk
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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FIGURE 22. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
ST S-1 Pulse T emplate
1.2
1
0.8 Norm a liz e d Am plitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
0 -1 2 3 6 9 1 1 4 7 8 5 1 2 3 1. .9 .6 .5 .4 .8 .7 .3 .2 .1 0. 0. 0. 0. 0. 0. 0. 0. 1. 1. -0 -0 -0 -0 -0 -0 -0 -0 -0 1. 0. 4
Time, in UI
TABLE 4: STS-1 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS LOWER CURVE -0.85 < T < -0.38 -0.38 - 0.03 NORMALIZED AMPLITUDE
< T < 0.36
* T 0.5 1 + sin -- 1 + ---------- - 0.03 2 0.18
- 0.03 UPPER CURVE
0.36 < T < 1.4
-0.85 < T < -0.68 -0.68 < T < 0.26
0.03
* T 0.5 1 + sin -- 1 + ---------- + 0.03 0.34 2
0.26 < T < 1.4
0.1 + 0.61 x e-2.4[T-0.26]
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Transmit Intrinsic Jitter RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) Jitter Tolerance @ Jitter Frequency 400 KHz Signal Level to Declare Loss of Signal Signal Level to Clear Loss of Signal NOTE: The above values are at TA = 250C and VDD = 3.3 V 5%. 900 0.15 Refer to Table 10 Refer to Table 10 1100 feet UIpp 8.6 0.90 9.65 1.00 0.02 10.6 1.10 0.05 UIpp ns 0.90 1.00 1.10 Vpk 0.65 0.75 0.90 Vpk
FIGURE 23. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499
D S3 Pulse T em plate
1.2
1
0.8 Norm a liz e d Am plitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
0 1 2 3 4 5 6 7 8 9 1 1 2 3 1. -1 .3 .2 .5 .7 .9 .8 .6 .4 .1 0. 0. 0. 0. 0. 0. 0. 0. 0. 1. 1. -0 -0 -0 -0 -0 -0 -0 -0 -0 1. 4
Tim e , in UI
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 6: DS3 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS LOWER CURVE -0.85 < T < -0.36 -0.36 - 0.03
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NORMALIZED AMPLITUDE
< T < 0.36
* T 0.5 1 + sin -- 1 + ---------- - 0.03 2 0.18
- 0.03 UPPER CURVE
0.36 < T < 1.4
-0.85 < T < -0.68 -0.68 < T < 0.36
0.03
* T 0.5 1 + sin -- 1 + ---------- + 0.03 0.34 2
0.36 < T < 1.4
0.08 + 0.407 x e-1.84[T-0.36]
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499)
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Transmit Intrinsic Jitter RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) Jitter Tolerance @ 400 KHz (Cat II) Signal Level to Declare Loss of Signal Signal Level to Clear Loss of Signal NOTE: The above values are at TA = 250C and VDD = 3.3V 5%. 900 0.15 Refer to Table 10 Refer to Table 10 1100 feet UIpp 10.10 0.90 11.18 1.00 0.02 12.28 1.10 0.05 UIpp ns 0.90 1.00 1.10 Vpk 0.65 0.75 0.85 Vpk
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
3.6
Transmit Drive Monitor
This feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on the line or a defective line driver. To activate this function, connect MTIP_n pins to the TTIP_n lines via a 270 resistor and MRing_n pins to TRing_n lines via 270 resistor as shown in Figure 24.
FIGURE 24. TRANSMIT DRIVER MONITOR SET-UP.
R1
TTIP(n)
31.6 +1%
R2
R3 75 1:1
TxPOS(n) TxNEG(n) TxLineClk(n)
TRing(n)
TPData(n) TNData(n) TxClk(n)
31.6 + 1%
R1
MTIP(n)
270
R2
MRing(n)
270
When the MTIP_n and MRing_n are connected to the TTIP_n and TRing_n lines, the drive monitor circuit monitors the line for transitions. The DMO_n (Drive Monitor Output) will be asserted "Low" as long as the transitions on the line are detected via MTIP_n and MRing_n. If no transitions on the line are detected for 128 32 TxClk_n periods, the DMO_n output toggles "High" and when the transitions are detected again, DMO_n toggles "Low".
NOTE: The Drive Monitor Circuit is only for diagnostic purpose and does not have to be used to operate the transmitter.
3.7
Transmitter Section On/Off
The transmitter section of each channel can either be turned on or off. To turn on the transmitter, set the input pin TxON to "High" and write a "1" to the TxON_n control bit. When the transmitter is turned off, TTIP_n and TRing_n are tri-stated.
NOTES: 1. 2. This feature provides support for Redundancy. To permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a "1" to the TxON_n control bits transfers the control to TxON pin.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 4.0 JITTER
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There are three fundamental parameters that describe circuit performance relative to jitter
* Jitter Tolerance * Jitter Transfer * Jitter Generation
4.1 JITTER TOLERANCE
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error rate (BER). To measure the jitter tolerance as shown in Figure 25, jitter is introduced by the sinusoidal modulation of the serial data bit sequence. Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as a combination of points. Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter frequency.
FIGURE 25. JITTER TOLERANCE MEASUREMENTS
Pattern Generator
Data
DUT XRT75L06D
Error Detector
Clock Modulation Freq.
FREQ Synthesizer
4.1.1
DS3/STS-1 Jitter Tolerance Requirements
Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 26 shows the jitter tolerance curve as per GR-499 specification.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FIGURE 26. INPUT JITTER TOLERANCE FOR DS3/STS-1
64 41 15 JITTER AMPLITUDE (UIpp) 10 5 1.5 0.3 0.15 0.1
GR-253 STS-1 GR-499 Cat II GR-499 Cat I XRT75L06D
0.01
0.03
0.3
2
20
100
JITTER FREQUENCY (kHz)
4.1.2
E3 Jitter Tolerance Requirements
ITU-T G.823 standard specifies that the clock and data recovery unit must be able to tolerate jitter up to certain specified limits. Figure 27 shows the tolerance curve.
FIGURE 27. INPUT JITTER TOLERANCE FOR E3
64 JITTER AMPLITUDE (UIpp) 10 1.5
ITU-T G.823 XRT75L06D
0.3
0.1
1 JITTER FREQUENCY (kHz)
10
800
As shown in the Figures above, in the jitter tolerance measurement, the dark line indicates the minimum level of jitter that the E3/DS3/STS-1 compliant component must tolerate. Table 8 below shows the jitter amplitude versus the modulation frequency for various standards.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
BIT RATE (KB/S) 34368 44736 44736 51840 INPUT JITTER AMPLITUDE (UI P-P) STANDARD A1 ITU-T G.823 GR-499 CORE Cat I GR-499 CORE Cat II GR-253 CORE Cat II 1.5 5 10 15 A2 0.15 0.1 0.3 1.5 A3 0.15
F1(HZ) F2(HZ) F3(KHZ) F4(KHZ) F5(KHZ)
MODULATION FREQUENCY
100 10 10 10
1000 2.3k 669 30
10 60 22.3 300
800 300 300 2
20
4.2
JITTER TRANSFER
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as the highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a low bandwidth loop, typically using a voltage-controlled crystal oscillator (VCXO). The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter. Table 9 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES
E3 ETSI TBR-24 DS3 GR-499 CORE section 7.3.2 Category I and Category II STS-1 GR-253 CORE section 5.6.2.1
NOTE: The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates.
4.3
Jitter Attenuator
An advanced crystal-less jitter attenuator per channel is included in the XRT75L06D. The jitter attenuator requires no external crystal nor high-frequency reference clock. By clearing or setting the JATx/Rx_n bits in the channel control registers selects the jitter attenuator either in the Receive or Transmit path on per channel basis. The FIFO size can be either 16-bit or 32-bit. The bits JA0_n and JA1_n can be set to appropriate combination to select the different FIFO sizes or to disable the Jitter Attenuator on a per channel basis. Data is clocked into the FIFO with the associated clock signal (TxClk or RxClk) and clocked out of the FIFO with the dejittered clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL_n is set to "1" in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts of jitter. Table 10 specifies the jitter transfer mask requirements for various data rates:
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 10: JITTER TRANSFER PASS MASKS
RATE (KBITS) 34368 44736
MASK G.823 ETSI-TBR-24 GR-499, Cat I GR-499, Cat II GR-253 CORE GR-253 CORE
F1 (HZ) 100
F2 (HZ) 300
F3 (HZ) 3K
F4 (KHZ) 800K
A1(dB) 0.5
A2(dB) -19.5
10 10 10 10
10k 56.6k 40 40k
-
15k 300k 15k 400k
0.1 0.1 0.1 0.1
-
51840
The jitter attenuator within the XRT75L06D meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the Figure 28.
FIGURE 28. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
JITTER AMPLITUDE
A1 A2
F1
F2
F3
F4
J IT T E R F R E Q U E N C Y (k H z )
4.3.1
JITTER GENERATION
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set according to the data rate. In general, the jitter is measured over a band of frequencies.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 5.0 DIAGNOSTIC FEATURES 5.1 PRBS Generator and Detector
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The XRT75L06D contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for diagnostic purpose. With the PRBSEN_n bit = "1", the transmitter will send out PRBS of 223-1 in E3 rate or 215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detector is also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go "Low" to indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the PRBSLS bit will be set to "1" and RNEG/LCV pin will go "High". With the PRBS mode enabled, the user can also insert a single bit error by toggling "INSPRBS" bit. This is done by writing a "1" to INSPRBS bit. The receiver at RNEG/LCV pin will pulse "High" for one RxClk cycle for every bit error detected. Any subsequent single bit error insertion must be done by first writing a "0" to INSPRBS bit and followed by a "1". Figure 29 shows the status of RNEG/LCV pin when the XRT75L06D is configured in PRBS mode.
NOTE: In PRBS mode, the device is forced to operate in Single-Rail Mode.
FIGURE 29. PRBS MODE
RxClk
SYNC LOSS
RxNEG/LCV
PRBS SYNC Single Bit Error
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
5.2
LOOPBACKS
The XRT75L06D offers three loopback modes for diagnostic purposes. The loopback modes are selected via the RLB_n and LLB_n bits n the Channel control registers select the loopback modes.
5.2.1 ANALOG LOOPBACK
In this mode, the transmitter outputs TTIP_n and TRing_n are internally connected to the receiver inputs RTIP_n and RRing_n as shown in Figure 30. Data and clock are output at RxClk_n, RxPOS_n and RxNEG_n pins for the corresponding transceiver. Analog loopback exercises most of the functional blocks of the device including the jitter attenuator which can be selected in either the transmit or receive path.
NOTES: 1. 2. In the Analog loopback mode, data is also output via TTIP_n and TRing_n pins. Signals on the RTIP_n and RRing_n pins are ignored during analog loopback.
FIGURE 30. ANALOG LOOPBACK
TxClk TxPOS TxNEG HDB3/B3ZS ENCODER
JITTER ATTENUATOR
TIMING CONTROL
TTIP Tx TRing
RxClk RxPOS RxNEG HDB3/B3ZS DECODER
JITTER ATTENUATOR
DATA & CLOCK RECOVERY
RTIP Rx RRing
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 5.2.2 DIGITAL LOOPBACK
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When the Digital Loopback is selected, the transmit clock TxClk_n and transmit data inputs (TxPOS_n & TxNEG_n are looped back and output onto the RxClk_n, RxPOS_n and RxNEG_n pins as shown in Figure 31.
FIGURE 31. DIGITAL LOOPBACK
TxCLK TxPOS TxNEG HDB3/B3ZS ENCODER
JITTER ATTENUATOR
TIMING CONTROL
TTIP Tx TRing
RxCLK RxPOS RxNEG HDB3/B3ZS DECODER
JITTER ATTENUATOR
DATA & CLOCK RECOVERY
RTIP Rx RRing
5.2.3
REMOTE LOOPBACK
With Remote loopback activated as shown in Figure 32, the receive data on RTIP and RRing is looped back after the jitter attenuator (if selected in receive or transmit path) to the transmit path using RxClk as transmit timing. The receive data is also output via the RxPOS and RxNEG pins.
NOTE: Input signals on TxClk, TxPOS and TxNEG are ignored during Remote loopback.
FIGURE 32. REMOTE LOOPBACK
TxCLK TxPOS TxNEG HDB3/B3ZS ENCODER
JITTER ATTENUATOR
TIMING CONTROL
TTIP Tx TRing
RxCLK RxPOS RxNEG HDB3/B3ZS DECODER
JITTER ATTENUATOR
DATA & CLOCK RECOVERY
RTIP Rx RRing
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
5.3
TRANSMIT ALL ONES (TAOS)
Transmit All Ones (TAOS) can be set by setting the TAOS_n control bits to "1" in the Channel control registers. When the TAOS is set, the Transmit Section generates and transmits a continuous AMI all "1's" pattern on TTIP_n and TRing_n pins. The frequency of this ones pattern is determined by TxClk_n. the TAOS data path is shown in Figure 33. TAOS does not operate in Analog loopback or Remote loopback modes, however will function in Digital loopback mode.
FIGURE 33. TRANSMIT ALL ONES (TAOS)
TxCLK TxPOS TxNEG HDB3/B3ZS ENCODER
JITTER ATTENUATOR
TIMING CONTROL
Tx
TTIP Transmit All 1's TRing
TAOS
RxCLK RxPOS RxNEG HDB3/B3ZS DECODER
JITTER ATTENUATOR
DATA & CLOCK RECOVERY
RTIP Rx RRing
41
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 6.0 MICROPROCESSOR INTERFACE BLOCK
xr
REV. 1.0.4
The Microprocessor Interface section supports communication between the local microprocessor (P) and the LIU. The XRT75L06D supports a parallel interface asynchronously or synchronously timed to the LIU. The microprocessor interface is selected by the state of the Pmode input pin. Selecting the microprocessor interface mode is shown in Table 11.
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE
PMODE "Low" "High" MICROPROCESSOR MODE Asynchronous Mode Synchronous Mode
The local P configures the LIU by writing data into specific addressable, on-chip Read/Write registers. The P provides the signals which are required for a general purpose microprocessor to read or write data into these registers. The P also supports polled and interrupt driven environments. A simplified block diagram of the microprocessor is shown in Figure 34.
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK
CS WR RD
Addr[7:0] D[7:0] PCLK Pmode RESET RDY INT
Microprocessor Interface
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS The LIU may be configured into different operating modes and have its performance monitored by software through a standard microprocessor using data, address and control signals. These interface signals are described below in Table 12. The microprocessor interface can be configured to operate in Asynchronous mode or Synchronous mode. TABLE 12: XRT75L06D MICROPROCESSOR INTERFACE SIGNALS
PIN NAME TYPE I I/O I DESCRIPTION Microprocessor Interface Mode Select Input pin This pin is used to specify the microprocessor interface mode. Bi-Directional Data Bus for register "Read" or "Write" Operations. Eight-Bit Address Bus Inputs The XRT75L06D LIU microprocessor interface uses a direct address bus. This address bus is provided to permit the user to select an on-chip register for Read/Write access. Chip Select Input This active low signal selects the microprocessor interface of the XRT75L06D LIU and enables Read/Write operations with the on-chip register locations. Read Signal This active low input functions as the read signal from the local P. When this pin is pulled "Low" (if CS is "Low") the LIU is informed that a read operation has been requested and begins the process of the read cycle. Write Signal This active low input functions as the write signal from the local P. When this pin is pulled "Low" (if CS is "Low") the LIU is informed that a write operation has been requested and begins the process of the write cycle. Ready Output This active low signal is provided by the LIU device. It indicates that the current read or write cycle is complete, and the LIU is waiting for the next command. Interrupt Output This active low signal is provided by the LIU to alert the local mP that a change in alarm status has occured. This pin is Reset Upon Read (RUR) once the alarm status registers have been cleared. Reset Input This active low input pin is used to Reset the LIU.
Pmode
D[7:0] Addr[7:0]
CS
I
RD
I
WR
I
RDY INT
O O
RESET
I
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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REV. 1.0.4
6.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The synchronous mode requires an input clock (PCLK) to be used as the microprocessor timing reference. Read and Write operations are described below. Read Cycle (For Pmode = "0" or "1")
Whenever the local P wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins Addr[7:0]. 2. While the P is placing this address value on the address bus, the address decoding circuitry should assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the P and the LIU microprocessor interface block. 3. Next, the P should indicate that this current bus cycle is a Read operation by toggling the RD input pin "Low". This action enables the bi-directional data bus output drivers of the LIU. 4. After the P toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this to inform the P that the data is available to be read by the P, and that it is ready for the next command. 5. After the P detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the RD input pin "High". 6. The CS input pin must be pulled "High" before a new command can be issued. Write Cycle (For Pmode = "0" or "1")
Whenever a local P wishes to write a byte or word of data into a register within the LIU, it should do the following.
1. Place the address of the target register on the address bus input pins Addr[7:0]. 2. While the P is placing this address value on the address bus, the address decoding circuitry should assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the P and the LIU microprocessor interface block. 3. The P should then place the byte or word that it intends to write into the target register, on the bi-directional data bus D[7:0]. 4. Next, the P should indicate that this current bus cycle is a Write operation by toggling the WR input pin "Low". This action enables the bi-directional data bus input drivers of the LIU. 5. After the P toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this to inform the P that the data has been written into the internal register location, and that it is ready for the next command. 6. The CS input pin must be pulled "High" before a new command can be issued.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FIGURE 35. ASYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
t0 Addr[7:0] Valid Address t0 Valid Address
WRITE OPERATION
CS
D[7:0] t1 RD
Valid Data for Readback
Data Available to Write Into the LIU
t3 WR t2 t4 RDY
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS
SYMBOL t0 t1 t2 NA t3 t4 NA PARAMETER Valid Address to CS Falling Edge CS Falling Edge to RD Assert RD Assert to RDY Assert RD Pulse Width (t2) CS Falling Edge to WR Assert WR Assert to RDY Assert WR Pulse Width (t4) MIN 0 0 70 0 70 MAX 65 65 ns ns ns ns ns ns ns UNITS
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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REV. 1.0.4
FIGURE 36. SYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
PCLK t0 Addr[7:0] Valid Address t0 Valid Address
WRITE OPERATION
CS
D[7:0] t1 RD
Valid Data for Readback
Data Available to Write Into the LIU
t3 WR t2 t4 RDY
TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS
SYMBOL t0 t1 t2 NA t3 t4 NA PARAMETER Valid Address to CS Falling Edge CS Falling Edge to RD Assert RD Assert to RDY Assert RD Pulse Width (t2) CS Falling Edge to WR Assert WR Assert to RDY Assert WR Pulse Width (t4) PCLK Period PCLK Duty Cycle PCLK "High/Low" time NOTE: 1. This timing parameter is based on the frequency of the synchronous clock (PCLK). To determine the access time, use the following formula: (PCLKperiod * 2) + 5ns MIN 0 0 40 0 40 15 MAX 35 35 ns ns ns, see note 1 ns ns ns, see note 1 ns ns UNITS
46
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FIGURE 37. INTERRUPT PROCESS
ERROR CONDITION OCCURS
Interrupt enable bits at 0x60 and 0xn1 set?
NO
YES
Interrupt status bits at 0x61 and 0xn2 set.
Interrupt Generated INT pin goes "Low"
Interrupt Service Routine reads the status register at 0x61
Interrupt Service Routine reads the status register at 0xn2
Interrupt is being serviced.
YES
Interrupt Pending ?
NO
INT pin goes "High" Normal Operation
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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REV. 1.0.4
6.2.1 Hardware Reset: The hardware reset is initiated by pulling the RESET pin "Low" for a minimum of 5 s. After the RESET pin is released, the register values are put in default states.
TABLE 15: REGISTER MAP AND BIT NAMES
ADDRESS (HEX) 0x00 0x08 0x60 0x61 0x62 0x6D 0x6E 0x6F Chip_id (read only) Chip_revision _id (read only) 0 1 0 1 PARAMETER NAME APS/Redundancy #1 APS/ Redundancy #2 Interrupt Enable (read/write) Interrupt Status (read only) DATA BITS 7 Reserved Reserved Reserved Reserved 6 5 TxON_5 RxON_5 4 TxON_4 RxON_4 3 TxON_3 RxON_3 2 TxON_2 RxON_2 1 TxON-1 RxON_1 0 TxON_0 RxON_0
INTEN_5 INTEN_4 INTEN_3 INTEN_2 INTEN_1 INTEN_0 INTST_5 INTST_4 INTST_3 INTST_2 INTST_1 INTST_0
Reserved 0 1 1 0
Chip version number
48
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL
ADDRESS (HEX) 0x00
TYPE R/W
REGISTER NAME APS # 1
SYMBOL TxON_n
DESCRIPTION Table below shows the status of the transmitter based on the bit and pin setting.
DEFAULT VALUE 0
Bit 0 0 1 1 0x08 0x60 0x61 R/W R/W ROR APS # 2 Interrupt Enable Interrupt Status RxON_n INTEN_n INTST_n
Pin 0 1 0 1
Transmitter Status OFF OFF OFF ON 0 0 0
Set this bit to turn on individual Receiver. Set this bit to enable the interrupts on per channel basis. Bits are set when an interrupt occurs.The respective source level interrupt status registers are read to determine the cause of interrupt. Reserved
0x62 0x6D 0x6E 0x6F R R Device _ id Version Number Chip_id
This read only register contains device id.
01010110
Chip_version This read only register contains chip version number
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5)
ADDRESS (HEX) 0x01 (ch 0) 0x11 (ch 1) 0x21 (ch 2) 0x31 (ch 3) 0x41 (ch 4) 0x51 (ch 5) PARAMETER NAME Interrupt Enable (read/write) DATA BITS 7 Reserved 6 5 4 3 FLIE_n 2 1 0
PRBSER PRBSERI CNTIE_n E_n
RLOLIE_n RLOSIE_ DMOIE_n n
0x02 (ch 0) Interrupt 0x12 (ch 1) Status 0x22 (ch 2) (reset on read) 0x32 (ch 3) 0x42 (ch 4) ox52 (ch 5)
Reserved
PRBSER PRBSERI CNTIS_n S_n
FLIS_n
RLOLIS_n RLOSIS_ DMOIS_n n
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TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5)
ADDRESS (HEX) 0x03 (ch 0) 0x13 (ch 1) 0x23 (ch 2) 0x33 (ch 3) 0x43 (ch 4) 0x53 (ch 5) 0x04 (ch 0) 0x14 (ch 1) 0x24 (ch 2) 0x34 (ch 3) 0x44 (ch 4) 0x54 (ch 5) 0x05 (ch 0) 0x15 (ch 1) 0x25 (ch 2) 0x35 (ch 3) 0x45 (ch 4) 0x55 (ch 5) 0x06 (ch 0) 0x16 (ch 1) 0x26 (ch 2) 0x36 (ch 3) 0x46 (ch 4) 0x56 (ch 5) 0x07 (ch 0) 0x17 (ch 1) 0x27 (ch 2) 0x37 (ch 3) 0x47 (ch 4) 0x57 (ch 5) 0x0A (ch 0) 0x1A (ch 1) 0x2A (ch 2) 0x3A (ch 3) 0x4A (ch 4) 0x5A (ch 5) 0x0B (ch 0) 0x1B (ch 1) 0x2B (ch 2) 0x3B (ch 3) 0x4B (ch 4) 0x5B (ch 5) PARAMETER NAME Alarm Status (read only) DATA BITS 7 6 5 4 ALOS_n 3 FL_n 2 RLOL_n 1 RLOS_n 0 DMO_n
Reserved PRBSLS_n DLOS_n
Transmit Control (read/write)
Reserved
TxMON_n INSPRBS Reserved _n
TAOS_n TxCLKINV TxLEV_n _n
Receive Control (read/write)
Reserved
DLOSDIS ALOSDIS RxCLKIN LOSMUT_ RxMON_n REQEN_ _n _n V_n n n
Block Control Reserved CLKOUTE PRBSEN_ (read/write) N_n 0
RLB_n
LLB_n
E3_n
STS1/ DS3_n
SR/DR_n
Jitter Attenuator Control (read/write)
Reserved
DFLCK_n PNTRST_ n
JA1_n
JATx/ Rx_n
JA0_n
PRBS Error Count Reg. MSB
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
PRBS Error Count Reg. LSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0C (ch 0) PRBS Error 0x1C (ch 1) Count Holding 0x2C (ch 2) Register 0x3C (ch 3) 0x4C (ch 4) 0x5C (ch 5)
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TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS (HEX) TYPE REGISTER NAME BIT# D0 SYMBOL DMOIE_n DESCRIPTION If the Driver Monitor (connected to the output of the channel) detects the absence of pulses for 128 consecutive cycles, it will set the interrupt flag if this bit has been set. DEFAULT VALUE 0
D1 0x01 (ch 0) 0x11 (ch 1) 0x21 (ch 2) 0x31 (ch 3) 0x41 (ch 4) 0x51 (ch 5) R/W Interrupt Enable (source level)
RLOSIE_n This flag will allow a loss of receive signal(for that channel) to send an interrupt to the Host when this bit is set. RLOLIE_n This flag will allow a loss of lock condition to send an interrupt to the Host when this bit is set. FLIE_n Set this bit to enable the interrupt when the FIFO Limit of the Jitter Attenuator is within 2 bits of overflow/underflow condition. NOTE: This bit field is ignored when the Jitter Attenuator is disabled.
0
D2 D3
0 0
D4 D5 D6-D7 D0
PRBSERIE Set this bit to enable the interrupt when the PRBS _n error is detected. PRBSERC Set this bit to enable the interrupt when the PRBS NTIE_n error count register saturates. Reserved DMOIS_n If the Drive monitor circuot detects the absence of pulses for 128 consecutive cycles, t will set this interrupt status flag (if enabled) This bit is set on a change of state of the DMO circuit.
0 0
0
D1 0x02 (ch 0) Reset Interrupt 0x12 (ch 1) on Status 0x22 (ch 2) Read (source 0x32 (ch 3) level) 0x42 (ch 4) 0x52 (ch 5) D2
RLOSIS_n This flag will indicate a change of "loss of Receive signal" to the Host when this bit is set. RLOLIS_n This flag will allow a change in the loss of lock condition to send an interrupt to the Host when this bit is enabled.Loss of lock is defined as a difference of greater than 0.5% between the recovered clock and the channel's reference clock. Any change (return to lock) will trigger the interrupt status flag again. FLIS_n This bit will generate an interrupt if the jitter attenuator FIFO reaches (or leaves) a limit condition. This limit condition is defined as the FIFO being within two counts of full or empty.
0 0
D3
0
D4 D5 D7-D6
PRBSERIS This bit is set when the PRBS error occurs. _n PRBSERC This bit is set when the PRBS error count register NTIS_n saturates. Reserved
0 0
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS (HEX) TYPE REGISTER NAME BIT# D0 SYMBOL DMO_n DESCRIPTION
xr
REV. 1.0.4
DEFAULT VALUE 0
This bit is set when no transitions on the TTIP/ TRING have been detected for 128 32 TxCLK periods.It will be cleared when pulses resume. This bit is set every time the receiver declares an LOS condition.It will be cleared when the signal is recognized again. This bit is set when the detected clock is greater than 0.5% oof frequency from the reference clock.By definition, the two frequencies are "not in lock" with each other. It will be cleared when they are "in lock" again.. This bit is set when the FIFO reaches its limit.The limit is defined to be within two bits of either underflow or overflow. This bit is set when the receiver declares that the Analog signal has degraded to the point that the signal has been lost. This bit is set when no input signals have been received for 10 to 255 bit times in E3 or 100 to 250 bit times in DS3 or STS-1 modes.This is a complete lack of incoming pulses rather than signal attenuation (ALOS). It should be noted that this time period is built into the Analog detector for E3 mode. Even though DS3/STS-1 mode does not require analog detection level, but it is provided and could help to determine the "quality of the line" for DS/STS-1 applications.
D1
RLOS_n
0
D2 0x03 (ch 0) 0x13 (ch 1) 0x23 (ch 2) 0x33 (ch 3) 0x43 (ch 4) 0x53 (ch 5) Read Alarm StaOnly tus
RLOL_n
0
D3
FL_n
0
D4
ALOS_n
0
D5
DLOS_n
0
D6
PRBSLS_n This bit is set when the PRBS detector has been enabled and it is not in sync with the incoming data pattern. Once the sync is achieved, it will be cleared. Reserved
0
D7
52
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS (HEX)
TYPE
REGISTER NAME
BIT# D0
SYMBOL TxLEV_n
DESCRIPTION This bit should be set when the transmitter is driving a line greater than 225 feet in the DS3 or STS-1 modes. It is not active in E3 mode.
DEFAULT VALUE 0
D1
TxCLKINV Set this bit to sample the data on TPOS/TNEG pins _n on the rising edge of TxCLK.Default is to sample on the falling edge of TxCLK. TAOS_n This bit should be set to transmit a continuous "all ones" data pattern. Timing will come from TxCLK if available otherwise from channel refernce clock. Reserved INSPRBS_ This bit causes a single bit error to be inserted in the n transmitted PRBS pattern if the PRBS generator/ detector has been enabled. TxMON_n When set, this bit enables the DMO circuit to monitor its own channel's transmit driver. Otherwise, it uses the MTIP/MRING pins to monitor another channel or device. Reserved REQEN_n This bit enables the Receiver Equalizer. When set, the equalizer boosts the high frequency components of the signal to make up for cable losses. NOTE: See section 5.01 for detailed description. RxMON_n Set this bit to place the Receiver in the monitoring mode. In this mode, it can process signals (at RTIP/ RRING) with 20dB of flat loss. This mode allows the channel to act as monitor of aline without loading the circuit. LOSMUT_ When set, the data on RPOS/RNEG is forced to n zero when LOS occurs. Thus any residual noise on the line is not output as spurious data. NOTE: If this bit has been set, it will remain set evan after the LOS condition is cleared. RxCLKINV When this bit is set, RPOS and RNEG will change _n on the falling edge of RCLK.Default is for the data to change on the rising edge of RCLK and be sampled by the terminal equipment on the falling edge of RCLK. ALOSDIS_ This bit is set to disable the ALOS detector. This flag n and the DLOSDIS are normally used in diagnostic mode. Normal operation of DS3 and STS-1 would have ALOS disabled. DLOSDIS_ This bit disables the digital LOS detector. This would n normally be disabled in E3 mode as E3 is a function of the level of the input. Reserved
0
0x04 (ch 0) 0x14 (ch 1) 0x24 (ch 2) 0x34 (ch 3) 0x44 (ch 4) 0x54 (ch 5)
R/W
Transmit Control
D2
0
D3 D4
0
D5
0
D7-D6 D0
0
D1 0x05 (ch 0) 0x15 (ch 1) 0x25 (ch 2) 0x35 (ch 3) 0x45 (ch 4) 0x55 (ch 5) R/W Receive Control D2
0
0
D3
0
D4
0
D5
0
D7-D6
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS (HEX) TYPE REGISTER NAME BIT# D0 SYMBOL SR/DR_n DESCRIPTION
xr
REV. 1.0.4
DEFAULT VALUE 0
Setting this bit configures the Receiver and Transmitter in Single-Rail (NRZ) mode. NOTE: See section 4.0 for detailed description. Setting this bit configures the channel into STS-1 mode. NOTE: This bit field is ignored if the channel is configured to operate in E3 mode. Setting this bit configures the channel in E3 mode. Setting this bit configures the channel in Local Loopback mode. This bit along with LLB_n determine the diagnostic mode as shown in the table below.
D1
STS-1/ DS3_n
0
D2 0x06 (Ch 0) 0x16 (Ch 1) 0x26 (Ch 2) 0x36 (ch 3) 0x46 (ch 4) 0x56 (ch 5) R/W Block Control D3 D4
E3_n LLB_n RLB_n
0 0 0
RLB_n 0 0 1 1
LLB_n 0 1 0 1
Loopback Mode Normal Operation Analog Local Remote Digital
D5
PRBSEN_ Setting this bit enables the PRBS generator/detecn tor. When in E3 mode, an unframed 223-1 pattern is used. For DS3 and STS-1, unframed 215-1 pattern is used. This mode of operation will use TCLK for timing. One should insure that a stable frequency is provided. Looping this signal back to its own receive channel and using RCLK to generate TCLK will cause an unstable condition and should be avoided. CLKOUTE Set this bit to enable the CLKOUTs on a per channel N_n basis. The frequency of the output clock is dependent on the configuration of the channels, either E3, DS3 or STS-1. Reserved
0
D6
0
D7
54
xr
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS (HEX)
TYPE
REGISTER NAME
BIT# D0
SYMBOL JA0_n
DESCRIPTION This bit along with JA1_n bit configures the Jitter Attenuator as shown in the table below.
DEFAULT VALUE 0
JA0_n 0
JA1_n 0 1 0 1
Mode 16 bit FIFO 32 bit FIFO SONET DE-SYNC mode Disable Jitter Attenuator
0x07 (Ch 0) 0x17 (Ch 1) 0x27 (Ch 2) 0x37 (ch 3) 0x47 (ch 4) 0x57 (ch 5)
R/W
Jitter Attenuator
0 1 1
D1 D2 D3
JATx/Rx_n Setting this bit selects the Jitter Attenuator in the Transmit Path. A "0" selects in the Receive Path. JA1_n This bit along with the JA0_n configures the Jitter Attenuator as shown in the table.
0 0 0
PNTRST_n Setting this bit resets the FIFO pointers to their initial state and flushes the FIFO. All existing FIFO data is lost. DFLCK_n Set this bit to "1" to disable fast locking of the PLL. This helps to reduce the time for the PLL to lock to incoming frequency when the Jitter Attenuator switches to narrow band. Reserved
D4
0
D7-D5
55
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
7.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU
The LIU with D-SYNC is very similar to the non D-SYNC LIU in that they both contain Jitter Attenuator blocks within each channel. They are also pin to pin compatible with each other. However, the Jitter Attenuators within the D-SYNC have some enhancements over and above those within the non D-SYNC device. The Jitter Attenuator blocks will support all of the modes and features that exist in the non D-SYNC device and in addition they also support a SONET/SDH De-Sync Mode.
NOTE: The "D" suffix within the part number stands for "De-Sync".
The SONET/SDH De-Sync feature of the Jitter Attenuator blocks permits the user to design a SONET/SDH PTE (Path Terminating Equipment) that will comply with all of the following Intrinsic Jitter and Wander requirements.
* For SONET Applications

Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 Applications) ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement Jitter and Wander Generation Requirements per ITU-T G.783 (for DS3 and E3 Applications)
* For SDH Applications
Specifically, if the user designs in the LIU along with a SONET/SDH Mapper IC (which can be realized as either a standard product or as a custom logic solution, in an ASIC or FPGA), then the following can be accomplished.
* The Mapper can receive an STS-N or an STM-M signal (which is carrying asynchronously-mapped DS3 and/
or E3 signals) and byte de-interleave this data into N STS-1 or 3*M VC-3 signals
* The Mapper will then terminate these STS-1 or VC-3 signals and will de-map out this DS3 or E3 data from
the incoming STS-1 SPEs or VC-3s, and output this DS3 or E3 to the DS3/E3 Facility-side towards the LIU
* This DS3 or E3 signal (as it is output from these Mapper devices) will contain a large amount of intrinsic jitter
and wander due to (1) the process of asynchronously mapping a DS3 or E3 signal into a SONET or SDH signal, (2) the occurrence of Pointer Adjustments within the SONET or SDH signal (transporting these DS3 or E3 signals) as it traverses the SONET/SDH network, and (3) clock gapping.
* When the LIU has been configured to operate in the "SONET/SDH De-Sync" Mode, then it will (1) accept this
jittery DS3 or E3 clock and data signal from the Mapper device (via the Transmit System-side interface) and (2) through the Jitter Attenuator, the LIU will reduce the Jitter and Wander amplitude within these DS3 or E3 signals such that they (when output onto the line) will comply with the above-mentioned intrinsic jitter and wander specifications.
7.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS
This section provides an in-depth discussion on the mechanisms that will cause Jitter and Wander within a DS3 or E3 signal that is being transported across a SONET or SDH Network. A lot of this material is introductory, and can be skipped by the engineer that is already experienced in SONET/SDH designs. In the wide-area network (WAN) in North America it is often necessary to transport a DS3 signal over a long distance (perhaps over a thousand miles) in order to support a particular service. Now rather than realizing this transport of DS3 data, by using over a thousand miles of coaxial cable (interspaced by a large number of DS3 repeaters) a common thing to do is to route this DS3 signal to a piece of equipment (such as a Terminal MUX, which in the "SONET Community" is known as a PTE or Path Terminating Equipment). This Terminal MUX will asynchronously map the DS3 signal into a SONET signal. At this point, the SONET network will now transport this asynchronously mapped DS3 signal from one PTE to another PTE (which is located at the other end of the SONET network). Once this SONET signal arrives at the remote PTE, this DS3 signal will then be extracted from the SONET signal, and will be output to some other DS3 Terminal Equipment for further processing. Similar things are done outside of North America. In this case, this DS3 or E3 signal is routed to a PTE, where it is asynchronously mapped into an SDH signal. This asynchronously mapped DS3 or E3 signal is then transported across the SDH network (from one PTE to the PTE at the other end of the SDH network). Once
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this SDH signal arrives at the remote PTE, this DS3 or E3 signal will then be extracted from the SDH signal, and will be output to some other DS3/E3 Terminal Equipment for further processing. Figure 38 presents an illustration of this approach to transporting DS3 data over a SONET Network
FIGURE 38. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK
SONET Network
DS3 Data
PTE PTE
PTE PTE
DS3 Data
As mentioned above a DS3 or E3 signal will be asynchronously mapped into a SONET or SDH signal and then transported over the SONET or SDH network. At the remote PTE this DS3 or E3 signal will be extracted (or de-mapped) from this SONET or SDH signal, where it will then be routed to DS3 or E3 terminal equipment for further processing. In order to insure that this "de-mapped" DS3 or E3 signal can be routed to any industry-standard DS3 or E3 terminal equipment, without any complications or adverse effect on the network, the Telcordia and ITU-T standard committees have specified some limits on both the Intrinsic Jitter and Wander that may exist within these DS3 or E3 signals as they are de-mapped from SONET/SDH. As a consequence, all PTEs that maps and de-mapped DS3/E3 signals into/from SONET/SDH must be designed such that the DS3 or E3 data that is de-mapped from SONET/SDH by these PTEs must meet these Intrinsic Jitter and Wander requirements. As mentioned above, the LIU can assist the System Designer (of SONET/SDH PTE) by ensuring that their design will meet these Intrinsic Jitter and Wander requirements. This section of the data sheet will present the following information to the user.
* Some background information on Mapping DS3/E3 signals into SONET/SDH and de-mapping DS3/E3
signals from SONET/SDH.
* A brief discussion on the causes of jitter and wander within a DS3 or E3 signal that mapped into a SONET/
SDH signal, and is transported across the SONET/SDH Network.
* A brief review of these Intrinsic Jitter and Wander requirements in both SONET and SDH applications. * A brief review on the Intrinsic Jitter and Wander measurement results (of a de-mapped DS3 or E3 signal)
whenever the LIU device is used in a system design.
* A detailed discussion on how to design with and configure the LIU device such that the end-system will meet
these Intrinsic Jitter and Wander requirements.
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In a SONET system, the relevant specification requirements for Intrinsic Jitter and Wander (within a DS3 signal that is mapped into and then de-mapped from SONET) are listed below.
* Telcordia GR-253-CORE Category I Intrinsic Jitter Requirements for DS3 Applications (Section 5.6), and * ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement
In general, there are three (3) sources of Jitter and Wander within an asynchronously-mapped DS3 signal that the system designer must be aware of. These sources are listed below.
* Mapping/De-Mapping Jitter * Pointer Adjustments * Clock Gapping
Each of these sources of jitter/wander will be defined and discussed in considerable detail within this Section. In order to accomplish all of this, this particular section will discuss all of the following topics in details.
* How DS3 data is mapped into SONET, and how this mapping operation contributes to Jitter and Wander
within this "eventually de-mapped" DS3 signal.
* How this asynchronously-mapped DS3 data is transported throughout the SONET Network, and how
occurrences on the SONET network (such as pointer adjustments) will further contributes to Jitter and Wander within the "eventually de-mapped" DS3 signal.
* A review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications * A review of the DS3 Wander requirements per ANSI T1.105.03b-1997 * A review of the Intrinsic Jitter and Wander Capabilities of the LIU in a typical system application * An in-depth discussion on how to design with and configure the LIU to permit the system to the meet the
above-mentioned Intrinsic Jitter and Wander requirements
NOTE: An in-depth discussion on SDH De-Sync Applications will be presented in the next revision of this data sheet.
7.2
MAPPING/DE-MAPPING JITTER/WANDER
Mapping/De-Mapping Jitter (or Wander) is defined as that intrinsic jitter (or wander) that is induced into a DS3 signal by the "Asynchronous Mapping" process. This section will discuss all of the following aspects of Mapping/De-Mapping Jitter.
* How DS3 data is mapped into an STS-1 SPE * How frequency offsets within either the DS3 signal (being mapped into SONET) or within the STS-1 signal
itself contributes to intrinsic jitter/wander within the DS3 signal (being transported via the SONET network).
7.2.1 HOW DS3 DATA IS MAPPED INTO SONET
Whenever a DS3 signal is asynchronously mapped into SONET, this mapping is typically accomplished by a PTE accepting DS3 data (from some remote terminal) and then loading this data into certain bit-fields within a given STS-1 SPE (or Synchronous Payload Envelope). At this point, this DS3 signal has now been asynchronously mapped into an STS-1 signal. In most applications, the SONET Network will then take this particular STS-1 signal and will map it into "higher-speed" SONET signals (e.g., STS-3, STS-12, STS-48, etc.) and will then transport this asynchronously mapped DS3 signal across the SONET network, in this manner. As this "asynchronously-mapped" DS3 signal approaches its "destination" PTE, this STS-1 signal will eventually be de-mapped from this STS-N signal. Finally, once this STS-1 signal reaches the "destination" PTE, then this asynchronously-mapped DS3 signal will be extracted from this STS-1 signal.
7.2.1.1 A Brief Description of an STS-1 Frame
In order to be able to describe how a DS3 signal is asynchronously mapped into an STS-1 SPE, it is important to define and understand all of the following.
* The STS-1 frame structure * The STS-1 SPE (Synchronous Payload Envelope)
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* Telcordia GR-253-CORE's recommendation on mapping DS3 data into an STS-1 SPE
An STS-1 frame is a data-structure that consists of 810 bytes (or 6480 bits). A given STS-1 frame can be viewed as being a 9 row by 90 byte column array (making up the 810 bytes). The frame-repetition rate (for an STS-1 frame) is 8000 frames/second. Therefore, the bit-rate for an STS-1 signal is (6480 bits/frame * 8000 frames/sec =) 51.84Mbps. A simple illustration of this SONET STS-1 frame is presented below in Figure 39.
FIGURE 39. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME
90 Bytes
9 Rows
STS-1 Frame (810 Bytes)
Last Byte of the STS-1 Frame First Byte of the STS-1 Frame
Figure 39 indicates that the very first byte of a given STS-1 frame (to be transmitted or received) is located in the extreme upper left hand corner of the 90 column by 9 row array, and that the very last byte of a given STS1 frame is located in the extreme lower right-hand corner of the frame structure. Whenever a Network Element transmits a SONET STS-1 frame, it starts by transmitting all of the data, residing within the top row of the STS1 frame structure (beginning with the left-most byte, and then transmitting the very next byte, to the right). After the Network Equipment has completed its transmission of the top or first row, it will then proceed to transmit the second row of data (again starting with the left-most byte, first). Once the Network Equipment has transmitted the last byte of a given STS-1 frame, it will proceed to start transmitting the very next STS-1 frame. The illustration of the STS-1 frame (in Figure 39) is very simplistic, for multiple reasons. One major reason is that the STS-1 frame consists of numerous types of bytes. For the sake of discussion within this data sheet, the STS-1 frame will be described as consisting of the following types (or groups) of bytes.
* The Transport Overheads (or TOH) Bytes * The Envelope Capacity Bytes
7.2.1.1.1
The Transport Overhead (TOH) Bytes
The Transport Overhead or TOH bytes occupy the very first three (3) byte columns within each STS-1 frame. Figure 40 presents another simple illustration of an STS-1 frame structure. However, in this case, both the TOH and the Envelope Capacity bytes are designated in this Figure.
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FIGURE 40. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
90 Bytes
3 Bytes
87 Bytes
TOH
Envelope Capacity
9 Row
Since the TOH bytes occupy the first three byte columns of each STS-1 frame, and since each STS-1 frame consists of nine (9) rows, then we can state that the TOH (within each STS-1 frame) consists of 3 byte columns x 9 rows = 27 bytes. The byte format of the TOH is presented below in Figure 41.
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3 Byte Columns
87 Byte Columns
A1 A1 B1 B1 D1 D1 H1 H1
9 Rows
A2 A2 E1 E1 D2 D2 H2 H2 K1 K1 D5 D5 D8 D8 D11 D11 M0 M0
C1 C1 F1 F1 D3 D3 H3 H3 K2 K2 D6 D6 D9 D9 D12 D12 E2 E2 The TOH Bytes
B2 B2 D4 D4 D7 D7 D10 D10 S1 S1
Envelope Capacity Envelope Capacity Bytes Bytes
In general, the role/purpose of the TOH bytes is to fulfill the following functions.
* To support STS-1 Frame Synchronization * To support Error Detection within the STS-1 frame * To support the transmission of various alarm conditions such as RDI-L (Line - Remote Defect Indicator) and
REI-L (Line - Remote Error Indicator)
* To support the Transmission and Reception of "Section Trace" Messages * To support the Transmission and Reception of OAM&P Messages via the DCC Bytes (Data Communication
Channel bytes - D1 through D12 byte) The roles of most of the TOH bytes is beyond the scope of this Data Sheet and will not be discussed any further. However, there are a three TOH bytes that are important from the stand-point of this data sheet, and will discussed in considerable detail throughout this document. These are the H1 and H2 (e.g., the SPE Pointer) bytes and the H3 (e.g., the Pointer Action) byte. Figure 42 presents an illustration of the Byte-Format of the TOH within an STS-1 Frame, with the H1, H2 and H3 bytes highlighted.
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FIGURE 42. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME
3 Byte Columns
87 Byte Columns
A1 A1 B1 B1 D1 D1 H1 H1
9 Rows
A2 A2 E1 E1 D2 D2 H2 H2 K1 K1 D5 D5 D8 D8 D11 D11 M0 M0
C1 C1 F1 F1 D3 D3 H3 H3 K2 K2 D6 D6 D9 D9 D12 D12 E2 E2 The TOH Bytes
B2 B2 D4 D4 D7 D7 D10 D10 S1 S1
Envelope Capacity Envelope Capacity Bytes Bytes
Although the role of the H1, H2 and H3 bytes will be discussed in much greater detail in "Section 7.3, Jitter/ Wander due to Pointer Adjustments" on page 69. For now, we will simply state that the role of these bytes is two-fold.
* To permit a given PTE (Path Terminating Equipment) that is receiving an STS-1 data to be able to locate the
STS-1 SPE (Synchronous Payload Envelope) within the Envelope Capacity of this incoming STS-1 data stream and,
* To inform a given PTE whenever Pointer Adjustment and NDF (New Data Flag) events occur within the
incoming STS-1 data-stream.
7.2.1.1.2
The Envelope Capacity Bytes within an STS-1 Frame
In general, the Envelope Capacity Bytes are any bytes (within an STS-1 frame) that exist outside of the TOH bytes. In short, the Envelope Capacity contains the STS-1 SPE (Synchronous Payload Envelope). In fact, every single byte that exists within the Envelope Capacity also exists within the STS-1 SPE. The only difference that exists between the "Envelope Capacity" as defined in Figure 41 and Figure 42 above and the STS-1 SPE is that the Envelope Capacity is aligned with the STS-1 framing boundaries and the TOH bytes; whereas the STS-1 SPE is NOT aligned with the STS-1 framing boundaries, nor the TOH bytes. The STS-1 SPE is an "87 byte column x 9 row" data-structure (which is the exact same size as is the Envelope Capacity) that is permitted to "float" within the "Envelope Capacity". As a consequence, the STS-1 SPE (within an STS-1 data-stream) will typically straddle across an STS-1 frame boundary.
7.2.1.1.3
The Byte Structure of the STS-1 SPE
As mentioned above, the STS-1 SPE is an 87 byte column x 9 row structure. The very first column within the STS-1 SPE consists of some overhead bytes which are known as the "Path Overhead" (or POH) bytes. The remaining portions of the STS-1 SPE is available for "user" data. The Byte Structure of the STS-1 SPE is presented below in Figure 43.
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87 Bytes 1 Byte 86 Bytes
9 Rows
J1 B3 C2 G1 F2 H4 Z3 Z4 Z5
Payload (or User) Data
In general, the role/purpose of the POH bytes is to fulfill the following functions.
* To support error detection within the STS-1 SPE * To support the transmission of various alarm conditions such as RDI-P (Path - Remote Defect Indicator) and
REI-P (Path - Remote Error Indicator)
* To support the transmission and reception of "Path Trace" Messages
The role of the POH bytes is beyond the scope of this data sheet and will not be discussed any further.
7.2.1.2 Mapping DS3 data into an STS-1 SPE
Now that we have defined the STS-1 SPE, we can now describe how a DS3 signal is mapped into an STS-1 SPE. As mentioned above, the STS-1 SPE is basically an 87 byte column x 9 row structure of data. The very first byte column (e.g., in all 9 bytes) consists of the POH (Path Overhead) bytes. All of the remaining bytes within the STS-1 SPE is simply referred to as "user" or "payload" data because this is the portion of the STS-1 signal that is used to transport "user data" from one end of the SONET network to the other. Telcordia GR-253CORE specifies the approach that one must use to asynchronously map DS3 data into an STS-1 SPE. In short, this approach is presented below in Figure 44.
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FIGURE 44. AN ILLUSTRATION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE
* For DS3 Mapping, the STS-1 SPE has the following structure.
87 bytes R R R R R R R R R R R R R R R R R R C1 C1 C1 C1 C1 C1 C1 C1 C1 25I 25I 25I 25I 25I 25I 25I 25I 25I R R R R R R R R R C2 C2 C2 C2 C2 C2 C2 C2 C2 I I I I I I I I I 25I 25I 25I 25I 25I 25I 25I 25I 25I
i = DS3 data
R R R R R R R R R
C3 C3 C3 C3 C3 C3 C3 C3 C3
I I I I I I I I I
25I 25I 25I 25I 25I 25I 25I 25I 25I
POH
I = [i, i, i, i, i, i, i, i] R = [r, r, r, r, r, r, r, r] C1 = [r, r, c, i, i, i, i, i] C2 = [c, c, r, r, r, r, r, r] C3 = [c, c, r, r, o, o, r, s]
Fixed Stuff
r = fixed stuff bit c = stuff control bit s = stuff opportunity bit o = overhead communications channel bit
Figure 44 was copied directly out of Telcordia GR-253-CORE. However, this figure can be simplified and redrawn as depicted below in Figure 45.
FIGURE 45. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO AN STS-1 SPE
18r 18r 18r 18r 18r 18r 18r 18r 18r
c c c c c c c c c
205i 205i 205i 205i 205i 205i 205i 205i 205i
16r 16r 16r 16r 16r 16r 16r 16r 16r
2c 2c 2c 2c 2c 2c 2c 2c 2c
6r 6r 6r 6r 6r 6r 6r 6r 6r
208i 208i 208i 208i 208i 208i 208i 208i 208i
16r 16r 16r 16r 16r 16r 16r 16r 16r
2c 2c 2c 2c 2c 2c 2c 2c 2c
2r 2r 2r 2r 2r 2r 2r 2r 2r
2o 2o 2o 2o 2o 2o 2o 2o 2o
1r 1r 1r 1r 1r 1r 1r 1r 1r
s s s s s s s s s
208i 208i 208i 208i 208i 208i 208i 208i 208i
POH
r c i s
- Fixed Stuff Bits - Stuff Control/Indicator Bits - DS3 Data Bits - Stuff Opportunity Bits
o
- Overhead Communication Bits
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Figure 45 presents an alternative illustration of Telcordia GR-253-CORE's recommendation on how to asynchronously map DS3 data into an STS-1 SPE. In this case, the STS-1 SPE bit-format is expressed purely in the form of "bit-types" and "numbers of bits within each of these types of bits". If one studies this figure closely he/she will notice that this is the same "87 byte column x 9 row" structure that we have been talking about when defining the STS-1 SPE. However, in this figure, the "user-data" field is now defined and is said to consist of five (5) different types of bits. Each of these bit-types play a role when asynchronously mapping a DS3 signal into an STS-1 SPE. Each of these types of bits are listed and described below.
Fixed Stuff Bits
Fixed Stuff bits are simply "space-filler" bits that simply occupy space within the STS-1 SPE. These bit-fields have no functional role other than "space occupation". Telcordia GR-253-CORE does not define any particular value that these bits should be set to. Each of the 9 rows, within the STS-1 SPE will contain 59 of these "fixed stuff" bits.
DS3 Data Bits
The DS3 Data-Bits are (as its name implies) used to transport the DS3 data-bits within the STS-1 SPE. If the STS-1 SPE is transporting a framed DS3 data-stream, then these DS3 Data bits will carry both the "DS3 payload data" and the "DS3 overhead bits". Each of the 9 rows, within the STS-1 SPE will contain 621 of these "DS3 Data bits". This means that each STS-1 SPE contains 5,589 of these DS3 Data bit-fields.
Stuff Opportunity Bits
The "Stuff" Opportunity bits will function as either a "stuff" (or junk) bit, or it will carry a DS3 data-bit. The decision as to whether to have a "Stuff Opportunity" bit transport a "DS3 data-bit" or a "stuff" bit depends upon the "timing differences" between the DS3 data that is being mapped into the STS-1 SPE and the timing source that is driving the STS-1 circuitry within the PTE. As will be described later on, these "Stuff Opportunity" Bits play a very important role in "frequency-justifying" the DS3 data that is being mapped into the STS-1 SPE. These "Stuff Opportunity" bits also play a critical role in inducing Intrinsic Jitter and Wander within the DS3 signal (as it is de-mapped by the remote PTE). Each of the 9 rows, within the STS-1 SPE consists of one (1) Stuff Opportunity bit. Hence, there are a total of nine "Stuff Opportunity" bits within each STS-1 SPE.
Stuff Control/Indicator Bits
Each of the nine (9) rows within the STS-1 SPE contains five (5) Stuff Control/Indicator bits. The purpose of these "Stuff Control/Indicator" bits is to indicate (to the de-mapping PTE) whether the "Stuff Opportunity" bits (that resides in the same row) is a "Stuff" bit or is carrying a DS3 data bit. If all five of these "Stuff Control/Indicator" bits, within a given row are set to "0", then this means that the corresponding "Stuff Opportunity" bit (e.g., the "Stuff Opportunity" bit within the same row) is carrying a DS3 data bit. Conversely, if all five of these "Stuff Control/Indicator" bits, within a given row are set to "1" then this means that the corresponding "Stuff Opportunity" bit is carrying a "stuff" bit.
Overhead Communication Bits
Telcordia GR-253-CORE permits the user to use these two bits (for each row) as some sort of "Communications" bit. Some Mapper devices, such as the XRT94L43 12-Channel DS3/E3/STS-1 to STS-12/ STM-1 Mapper and the XRT94L33 3-Channel DS3/E3/STS-1 to STS-3/STM-1 Mapper IC (both from Exar Corporation) do permit the user to have access to these bit-fields. However, in general, these particular bits can also be thought of as "Fixed Stuff" bits, that mostly have a "space occupation" function.
7.2.2 DS3 Frequency Offsets and the Use of the "Stuff Opportunity" Bits
In order to fully convey the role that the "stuff-opportunity" bits play, when mapping DS3 data into SONET, we will present a detailed discussion of each of the following "Mapping DS3 into STS-1" scenarios.
* The Ideal Case (e.g., with no frequency offsets) * The 44.736Mbps + 1 ppm Case
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* The 44.736MHz - 1ppm Case
Throughout each of these cases, we will discuss how the resulting "bit-stuffing" (that was done when mapping the DS3 signal into SONET) affects the amount of intrinsic jitter and wander that will be present in the DS3 signal, once it is ultimately de-mapped from SONET.
7.2.2.1 The Ideal Case for Mapping DS3 data into an STS-1 Signal (e.g., with no Frequency Offsets)
Let us assume that we are mapping a DS3 signal, which has a bit rate of exactly 44.736Mbps (with no frequency offset) into SONET. Further, let us assume that the SONET circuitry within the PTE is clocked at exactly 51.84MHz (also with no frequency offset), as depicted below.
FIGURE 46. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE
DS3_Data_In
STS-1_Data_Out
PTE PTE
44.736MHz + 0ppm 51.84MHz + 0ppm
Given the above-mentioned assumptions, we can state the following.
* The DS3 data-stream has a bit-rate of exactly 44.736Mbps * The PTE will create 8000 STS-1 SPE's per second * In order to properly map a DS3 data-stream into an STS-1 data-stream, then each STS-1 SPE must carry
(44.736Mbps/8000 =) 5592 DS3 data bits.
Is there a Problem?
According to Figure 45, each STS-1 SPE only contains 5589 bits that are specifically designated for "DS3 data bits". In this case, each STS-1 SPE appears to be three bits "short".
No there is a Simple Solution
No, earlier we mentioned that each STS-1 SPE consists of nine (9) "Stuff Opportunity" bits. Therefore, these three additional bits (for DS3 data) are obtained by using three of these "Stuff Opportunity" bits. As a consequence, three (3) of these nine (9) "Stuff Opportunity" bits, within each STS-1 SPE, will carry DS3 databits. The remaining six (6) "Stuff Opportunity" bits will typically function as "stuff" bits. In summary, for the "Ideal Case"; where there is no frequency offset between the DS3 and the STS-1 bit-rates, once this DS3 data-stream has been mapped into the STS-1 data-stream, then each and every STS-1 SPE will have the following "Stuff Opportunity" bit utilization.
3 "Stuff Opportunity" bits will carry DS3 data bits. 6 "Stuff Opportunity" bits will function as "stuff" bits
In this case, this DS3 signal (which has now been mapped into STS-1) will be transported across the SONET network. As this STS-1 signal arrives at the "Destination PTE", this PTE will extract (or de-map) this DS3 datastream from each incoming STS-1 SPE. Now since each and every STS-1 SPE contains exactly 5592 DS3 data bits; then the bit rate of this DS3 signal will be exactly 44.736Mbps (such as it was when it was mapped into SONET, at the "Source" PTE).
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As a consequence, no "Mapping/De-Mapping" Jitter or Wander is induced in the "Ideal Case".
7.2.2.2 The 44.736Mbps + 1ppm Case
The "above example" was a very ideal case. In reality, there are going to be frequency offsets in both the DS3 and STS-1 signals. For instance Bellcore GR-499-CORE mandates that a DS3 signal have a bit rate of 44.736Mbps 20ppm. Hence, the bit-rate of a "Bellcore" compliant DS3 signal can vary from the exact correct frequency for DS3 by as much of 20ppm in either direction. Similarly, many SONET applications mandate that SONET equipment use at least a "Stratum 3" level clock as its timing source. This requirement mandates that an STS-1 signal must have a bit rate that is in the range of 51.84 4.6ppm. To make matters worse, there are also provisions for SONET equipment to use (what is referred to as) a "SONET Minimum Clock" (SMC) as its timing source. In this case, an STS-1 signal can have a bit-rate in the range of 51.84Mbps 20ppm. In order to convey the impact that frequency offsets (in either the DS3 or STS-1 signal) will impose on the bitstuffing behavior, and the resulting bit-rate, intrinsic jitter and wander within the DS3 signal that is being transported across the SONET network; let us assume that a DS3 signal, with a bit-rate of 44.736Mbps + 1ppm is being mapped into an STS-1 signal with a bit-rate of 51.84Mbps + 0ppm. In this case, the following things will occur.
* In general, most of the STS-1 SPE's will each transport 5592 DS3 data bits. * However, within a "one-second" period, a DS3 signal that has a bit-rate of 44.736Mbps + 1 ppm will deliver
approximately 44.7 additional bits (over and above that of a DS3 signal with a bit-rate of 44.736Mbps + 0 ppm). This means that this particular signal will need to "negative-stuff" or map in an additional DS3 data bit every (1/44.736 =) 22.35ms. In other words, this additional DS3 data bit will need to be mapped into about one in every (22.35ms * 8000 =) 178.8 STS-1 SPEs in order to avoid dropping any DS3 data-bits.
What does this mean at the "Source" PTE?
All of this means that as the "Source" PTE maps this DS3 signal, with a data rate of 44.736Mbps + 1ppm into an STS-1 signal, most of the resulting "outbound" STS-1 SPEs will transport 5592 DS3 data bits (e.g., 3 Stuff Opportunity bits will be carrying DS3 data bits, the remaining 6 Stuff Opportunity bits are "stuff" bits, as in the "Ideal" case). However, in approximately one out of 178.8 "outbound" STS-1 SPEs, there will be a need to insert an additional DS3 data bit within this STS-1 SPE. Whenever this occurs, then (for these particular STS1 SPEs) the SPE will be carrying 5593 DS3 data bits (e.g., 4 Stuff Opportunity bits will be carrying DS3 data bits, the remaining 5 Stuff Opportunity bits are "stuff" bits). Figure 47 presents an illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, during this condition.
FIGURE 47. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL
Extra DS3 Data Bit Stuffed Here
SPE # N 5592 5592 DS3 Data DS3 Data Bits Bits
SPE # N+1 5592 5592 DS3 Data DS3 Data Bits Bits
SPE # N+177 5592 5592 DS3 Data DS3 Data Bits Bits 5593 5593 DS3 Data DS3 Data Bits Bits
SPE # N+179 5592 5592 DS3 Data DS3 Data Bits Bits
Source Source PTE PTE
SPE # N+178
44.736Mbps + 1ppm
STS-1 SPE Data Stream
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What does this mean at the "Destination" PTE?
In this case, this DS3 signal (which has now been mapped into an STS-1 data-stream) will be transported across the SONET network. As this STS-1 signal arrives at the "Destination" PTE, this PTE will extract (or demap) this DS3 data from each incoming STS-1 SPE. Now, in this case most (e.g., 177/178.8) of the incoming STS-1 SPEs will contain 5592 DS3 data-bits. Therefore, the nominal data rate of the DS3 signal being demapped from SONET will be 44.736Mbps. However, in approximately 1 out of every 178 incoming STS-1 SPEs, the SPE will carry 5593 DS3 data-bits. This means that (during these times) the data rate of the demapped DS3 signal will have an instantaneous frequency that is greater than 44.736Mbps. These "excursion" of the de-mapped DS3 data-rate, from the nominal DS3 frequency can be viewed as occurrences of "mapping/ de-mapping" jitter. Since each of these "bit-stuffing" events involve the insertion of one DS3 data bit, we can say that the amplitude of this "mapping/de-mapping" jitter is approximately 1UI-pp. From this point on, we will be referring to this type of jitter (e.g., that which is induced by the mapping and de-mapping process) as "demapping" jitter. Since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35ms, we can state that this jitter has a frequency of 44.7Hz.
7.2.2.3 The 44.736Mbps - 1ppm Case
In this case, let us assume that a DS3 signal, with a bit-rate of 44.736Mbps - 1ppm is being mapped into an STS-1 signal with a bit-rate of 51.84Mbps + 0ppm. In this case, the following this will occur.
* In general, most of the STS-1 SPEs will each transport 5592 DS3 data bits. * However, within a "one-second" period a DS3 signal that has a bit-rate of 44.736Mbps - 1ppm will deliver
approximately 45 too few bits below that of a DS3 signal with a bit-rate of 44.736Mbps + 0ppm. This means that this particular signal will need to "positive-stuff" or exclude a DS3 data bit from mapping every (1/44.736) = 22.35ms. In other words, we will need to avoid mapping this DS3 data-bit about one in every (22.35ms*8000) = 178.8 STS-1 SPEs.
What does this mean at the "Source" PTE?
All of this means that as the "Source" PTE maps this DS3 signal, with a data rate of 44.736Mbps - 1ppm into an STS-1 signal, most of the resulting "outbound" STS-1 SPEs will transport 5592 DS3 data bits (e.g., 3 Stuff Opportunity bits will be carrying DS3 data bits, the remaining 6 Stuff Opportunity bits are "stuff" bits). However, in approximately one out of 178.8 "outbound" STS-1 SPEs, there will be a need for a "positive-stuffing" event. Whenever these "positive-stuffing" events occur then (for these particular STS-1 SPEs) the SPE will carry only 5591 DS3 data bits (e.g., in this case, only 2 Stuff Opportunity bits will be carrying DS3 data-bits, and the remaining 7 Stuff Opportunity bits are "stuff" bits). Figure 48 presents an illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, during this condition.
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FIGURE 48. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL
DS3 Data Bit Excluded Here
SPE # N 5592 5592 DS3 Data DS3 Data Bits Bits
SPE # N+1 5592 5592 DS3 Data DS3 Data Bits Bits
SPE # N+177 5592 5592 DS3 Data DS3 Data Bits Bits 5591 5591 DS3 Data DS3 Data Bits Bits
SPE # N+179 5592 5592 DS3 Data DS3 Data Bits Bits
Source Source PTE PTE
SPE # N+178
44.736Mbps - 1ppm
STS-1 SPE Data Stream
What does this mean at the Destination PTE?
In this case, this DS3 signal (which has now been mapped into an STS-1 data-stream) will be transported across the SONET network. As this STS-1 signal arrives at the "Destination" PTE, this PTE will extract (or demap) this DS3 data from each incoming STS-1 SPE. Now, in this case, most (e.g., 177/178.8) of the incoming STS-1 SPEs will contain 5592 DS3 data-bits. Therefore, the nominal data rate of the DS3 signal being demapped from SONET will be 44.736Mbps. However, in approximately 1 out of every 178 incoming STS-1 SPEs, the SPE will carry only 5591 DS3 data bits. This means that (during these times) the data rate of the demapped DS3 signal will have an instantaneous frequency that is less than 44.736Mbps. These "excursions" of the de-mapped DS3 data-rate, from the nominal DS3 frequency can be viewed as occurrences of mapping/demapping jitter with an amplitude of approximately 1UI-pp. Since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35ms, we can state that this jitter has a frequency of 44.7Hz.
We talked about De-Mapping Jitter, What about De-Mapping Wander?
The Telcordia and Bellcore specifications define "Wander" as "Jitter with a frequency of less than 10Hz". Based upon this definition, the DS3 signal (that is being transported by SONET) will cease to contain jitter and will now contain "Wander", whenever the frequency offset of the DS3 signal being mapped into SONET is less than 0.2ppm.
7.3 Jitter/Wander due to Pointer Adjustments
In the previous section, we described how a DS3 signal is asynchronously-mapped into SONET, and we also defined "Mapping/De-mapping" jitter. In this section, we will describe how occurrences within the SONET network will induce jitter/wander within the DS3 signal that is being transported across the SONET network. In order to accomplish this, we will discuss the following topics in detail.
* The concept of an STS-1 SPE pointer * The concept of Pointer Adjustments * The causes of Pointer Adjustments * How Pointer Adjustments induce jitter/wander within a DS3 signal being transported by that SONET network.
7.3.1 The Concept of an STS-1 SPE Pointer
As mentioned earlier, the STS-1 SPE is not aligned to the STS-1 frame boundaries and is permitted to "float" within the Envelope Capacity. As a consequence, the STS-1 SPE will often times "straddle" across two
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consecutive STS-1 frames. consecutive STS-1 frames.
Figure 49 presents an illustration of an STS-1 SPE straddling across two
FIGURE 49. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES
TOH
STS-1 FRAME N
STS-1 FRAME N + 1
H1, H2 Bytes
J1 Byte (1st byte of SPE)
J1 Byte (1st byte of next SPE)
SPE can straddle across two STS-1 frames
A PTE that is receiving and terminating an STS-1 data-stream will perform the following tasks.
* It will acquire and maintain STS-1 frame synchronization with the incoming STS-1 data-stream. * Once the PTE has acquired STS-1 frame synchronization, then it will locate the J1 byte (e.g., the very byte
within the very next STS-1 SPE) within the Envelope Capacity by reading out the contents of the H1 and H2 bytes. The H1 and H2 bytes are referred to (in the SONET standards) as the SPE Pointer Bytes. When these two bytes are concatenated together in order to form a 16-bit word (with the H1 byte functioning as the "Most Significant Byte") then the contents of the "lower" 10 bit-fields (within this 16-bit word) reflects the location of the J1 byte within the Envelope Capacity of the incoming STS-1 data-stream. Figure 50 presents an illustration of the bit format of the H1 and H2 bytes, and indicates which bit-fields are used to reflect the location of the J1 byte.
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FIGURE 50. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION OF THE J1 BYTE, DESIGNATED
H1 Byte MSB
H2 Byte LSB
NNNNSSXXXXXXXXXX
10 Bit Pointer Expression
Figure 51 relates the contents within these 10 bits (within the H1 and H2 bytes) to the location of the J1 byte (e.g., the very first byte of the STS-1 SPE) within the Envelope Capacity.
FIGURE 51. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2 BYTES) AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS1 FRAME
TOH
The Pointer Value "0" is immediately After the H3 byte
A1 B1 D1 H1 B2 D4 D7 D10 S1
A2 E1 D2 H2 K1 D5 D8 D11 M0
C1/J0 F1 D3 H3 K2 D6 D9 D12 E2
522 609 696 0 87 174 261 348 435
523 610 697 1 88 175 262 349 436
******** ** ******** ***** ***** ******** ** ** ******** ** ******** ** ******** ***** ***** ******** ** **
607 694 781 85 172 259 346 433 520
608 695 782 86 173 260 347 434 521
NOTES: 1. 2. If the content of the "Pointer Bits" is "0x00" then the J1 byte is located immediately after the H3 byte, within the Envelope Capacity. If the contents of the 10-bit expression exceed the value of 0x30F (or 782, in decimal format) then it does not contain a valid pointer value.
7.3.2
Pointer Adjustments within the SONET Network
The word SONET stands for "Synchronous Optical NETwork. This name implies that the entire SONET network is synchronized to a single clock source. However, because the SONET (and SDH) Networks can
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span thousands of miles, traverse many different pieces of equipments, and even cross International boundaries; in practice, the SONET/SDH network is NOT synchronized to a single clock source. In practice, the SONET/SDH network can be thought of as being divided into numerous "Synchronization Islands". Each of these "Synchronization Islands" will consist of numerous pieces of SONET Terminal Equipment. Each of these pieces of SONET Terminal Equipment will all be synchronized to a single Stratum-1 clock source which is the most accurate clock source within the Synchronization Island. Typically a "Synchronization Island" will consist of a single "Timing Master" equipment along with multiple "Timing Slave" pieces of equipment. This "Timing Master" equipment will be directly connected to the Stratum-1 clock source and will have the responsibility of distributing a very accurate clock signal (that has been derived from the Stratum 1 clock source) to each of the "Timing Slave" pieces of equipment within the "Synchronization Island". The purpose of this is to permit each of the "Timing Slave" pieces of equipment to be "synchronized" with the "Timing Master" equipment, as well as the Stratum 1 Clock source. Typically this "clock distribution" is performed in the form of a BITS (Building Integrated Timing Supply) clock, in which a very precise clock signal is provided to the other pieces of equipment via a T1 or E1 line signal. Many of these "Synchronization Islands" will use a Stratum-1" clock source that is derived from GPS pulses that are received from Satellites that operate at Geo-synchronous orbit. Other "Synchronization Islands" will use a Stratum-1" clock source that is derived from a very precise local atomic clock. As a consequence, different "Synchronization Islands" will use different Stratum 1 clock sources. The up-shot of having these "Synchronization Islands" that use different "Stratum-1 clock" sources, is that the Stratum 1 Clock frequencies, between these "Synchronization Islands" are likely to be slightly different from each other. These "frequencydifferences" within Stratum 1 clock sources will result in "clock-domain changes" as a SONET signal (that is traversing the SONET network) passes from one "Synchronization Island" to another. The following section will describe how these "frequency differences" will cause a phenomenon called "pointer adjustments" to occur in the SONET Network.
7.3.3 Causes of Pointer Adjustments
The best way to discuss how pointer adjustment events occur is to consider an STS-1 signal, which is driven by a timing reference of frequency f1; and that this STS-1 signal is being routed to a network equipment (that resides within a different "Synchronization Island") and processes STS-1 data at a frequency of f2.
NOTE: Clearly, both frequencies f1 and f2 are at the STS-1 rate (e.g., 51.84MHz). However, these two frequencies are likely to be slightly different from each other.
Now, since the STS-1 signal (which is of frequency f1) is being routed to the network element (which is operating at frequency f2), the typical design approach for handling "clock-domain" differences is to route this STS-1 signal through a "Slip Buffer" as illustrated below.
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Clock Domain operating At frequency f1
STS-1 Data_IN STS-1 Clock_f1
STS-1 Data_OUT
SLIP BUFFER SLIP BUFFER
STS-1 Clock_f2
Clock Domain operating At Frequency f2.
In the "Slip Buffer, the "input" STS-1 data (labeled "STS-1 Data_IN") is latched into the FIFO, upon a given edge of the corresponding "STS-1 Clock_f1" input clock signal. The STS-1 Data (labeled "STS-1 Data_OUT") is clocked out of the Slip Buffer upon a given edge of the "STS-1 Clock_f2" input clock signal. The behavior of the data, passing through the "Slip Buffer" is now described for each possible relationship between frequencies f1 and f2.
If f1 = f2
If both frequencies, f1 and f2 are exactly equal, then the STS-1 data will be "clocked" into the "Slip Buffer" at exactly the same rate that it is "clocked out". In this case, the "Slip Buffer" will neither fill-up nor become depleted. As a consequence, no pointer-adjustments will occur in this STS-1 data stream. In other words, the STS-1 SPE will remain at a constant location (or offset) within each STS-1 envelope capacity for the duration that this STS-1 signal is supporting this particular service.
If f1 < f2
If frequency f1 is less than f2, then this means that the STS-1 data is being "clocked out" of the "Slip Buffer" at a faster rate than it is being clocked in. In this case, the "Slip Buffer" will eventually become depleted. Whenever this occurs, a typical strategy is to "stuff" (or insert) a "dummy byte" into the data stream. The purpose of stuffing this "dummy byte" is to compensate for the frequency differences between f1 and f2, and attempt to keep the "Slip Buffer, at a somewhat constant fill level.
NOTE: This "dummy byte" does not carry any valuable information (not for the user, nor for the system).
Since this "dummy byte" carries no useful information, it is important that the "Receiving PTE" be notified anytime this "dummy byte" stuffing occurs. This way, the Receiving Terminal can "know" not to treat this "dummy byte" as user data.
Byte-Stuffing and Pointer Incrementing in a SONET Network
Whenever this "byte-stuffing" occurs then the following other things occur within the STS-1 data stream.
During the STS-1 frame that contains the "Byte-Stuffing" event a. The "stuff-byte" will be inserted into the byte position immediately after the H3 byte. This insertion of the "dummy byte" immediately after the H3 byte position will cause the J1 byte (and in-turn, the rest of the SPE) to be "byte-shifted" away from the H3 byte. As a consequence, the offset between the H3 byte position and the STS-1 SPE will now have been increased by 1 byte. b. The "Transmitting" Network Equipment will notify the remote terminal of this byte-stuffing event, by inverting certain bits within the "pointer word" (within the H1 and H2 bytes) that are referred to as "I" bits.
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Figure 53 presents an illustration of the bit-format within the 16-bit word (consist of the H1 and H2 bytes) with the "I" bits designated.
FIGURE 53. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS DESIGNATED
H1 Byte MSB
H2 Byte LSB
NNNNSS IDID ID ID ID
10 Bit Pointer Expression
NOTE: At this time the "I" bits are inverted in order to denote that an "incrementing" pointer adjustment event is currently occurring.
During the STS-1 frame that follows the "Byte-Stuffing" event
The "I" bits (within the "pointer-word") will be set back to their normal value; and the contents of the H1 and H2 bytes will be incremented by "1".
If f1 > f2
If frequency f1 is greater than f2, then this means that the STS-1 data is being clocked into the "Slip Buffer" at a faster rate than is being clocked out. In this case, the "Slip Buffer" will start to fill up. Whenever this occurs, a typical strategy is to delete (e.g., negative-stuff) a byte from the Slip Buffer. The purpose of this "negativestuffing" is to compensate for the frequency differences between f1 and f2; and to attempt to keep the "Slip Buffer" at a somewhat constant fill-level.
NOTE: This byte, which is being "un-stuffed" does carry valuable information for the user (e.g., this byte is typically a payload byte). Therefore, whenever this negative stuffing occurs, two things must happen.
a. The "negative-stuffed" byte must not be simply discarded. In other words, it must somehow also be transmitted to the remote PTE with the remainder of the SPE data. b. The remote PTE must be notified of the occurrence of these "negative-stuffing" events. Further, the remote PTE must know where to obtain this "negative-stuffed" byte. Negative-Stuffing and Pointer-Decrementing in a SONET Network
Whenever this "byte negative-stuffing" occurs then the following other things occur within the STS-1 datastream.
During the STS-1 frame that contains the "Negative Byte-Stuffing" Event a. The "Negative-Stuffed" byte will be inserted into the H3 byte position. Whenever an SPE data byte is inserted into the H3 byte position (which is ordinarily an unused byte), the number of bytes that will exist between the H3 byte and the J1 byte within the very next SPE will be reduced by 1 byte. As a consequence, in this case, the J1 byte (and in-turn, the rest of the SPE) will now be "byte-shifted" towards the H3 byte position. b. The "Transmitting" Network Element will notify the remote terminal of this "negative-stuff" event by inverting certain bits within the "pointer word" (within the H1 and H2 bytes) that are referred to as "D" bits.
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Figure 54 presents an illustration of the bit format within the 16-bit word (consisting of the H1 and H2 bytes) with the "D" bits designated.
FIGURE 54. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS DESIGNATED
H1 Byte MSB
H2 Byte LSB
NNNNSS IDID ID ID ID
10 Bit Pointer Expression
NOTE: At this time the "D" bits are inverted in order to denote that a "decrementing" pointer adjustment event is currently occurring.
During the STS-1 frame that follows the "Negative Byte-Stuffing" Event
The "D" bits (within the pointer-word) will be set back to their normal value; and the contents of the H1 and H2 bytes will be decremented by one.
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7.3.4
Why are we talking about Pointer Adjustments?
The overall SONET network consists of numerous "Synchronization Islands". As a consequence, whenever a SONET signal is being transmitted from one "Synchronization Island" to another; that SONET signal will undergo a "clock domain" change as it traverses the network. This clock domain change will result in periodic pointer-adjustments occurring within this SONET signal. Depending upon the direction of this "clock-domain" shift that the SONET signal experiences, there will either be periodic "incrementing" pointer-adjustment events or periodic "decrementing" pointer-adjustment events within this SONET signal. Regardless of whether a given SONET signal is experiencing incrementing or decrementing pointer adjustment events, each pointer adjustment event will result in an abrupt 8-bit shift in the position of the SPE within the STS-1 data-stream. If this STS-1 signal is transporting an "asynchronously-mapped" DS3 signal; then this 8-bit shift in the location of the SPE (within the STS-1 signal) will result in approximately 8UIpp of jitter within the asynchronously-mapped DS3 signal, as it is de-mapped from SONET. In "Section 7.5, A Review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications" on page 77 we will discuss the "Category I Intrinsic Jitter Requirements (for DS3 Applications) per Telcordia GR-253-CORE. However, for now we will simply state that this 8UIpp of intrinsic jitter far exceeds these "intrinsic jitter" requirements. In summary, pointer-adjustments events are a "fact of life" within the SONET/SDH network. Further, pointeradjustment events, within a SONET signal that is transporting an asynchronously-mapped DS3 signal, will impose a significant impact on the Intrinsic Jitter and Wander within that DS3 signal as it is de-mapped from SONET.
7.4 Clock Gapping Jitter
In most applications (in which the LIU will be used in a SONET De-Sync Application) the user will typically interface the LIU to a Mapper Device in the manner as presented below in Figure 55.
FIGURE 55. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION
De-Mapped (Gapped) DS3 Data and Clock
TPDATA_n input pin
STS-N Signal
DS3 to STS-N DS3 to STS-N Mapper/ Mapper/ Demapper Demapper IC IC
LIU LIU
TCLK_n input
In this application, the Mapper IC will have the responsibility of receiving an STS-N signal (from the SONET Network) and performing all of the following operations on this STS-N signal.
* Byte-de-interleaving this incoming STS-N signal into N STS-1 signals * Terminating each of these STS-1 signals * Extracting (or de-mapping) the DS3 signal(s) from the SPEs within each of these terminated STS-1 signals.
In this application, these Mapper devices can be thought of as multi-channel devices. For example, an STS-3 Mapper can be viewed as a 3-Channel DS3/STS-1 to STS-3 Mapper IC. Similarly, an STS-12 Mapper can be
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viewed as a 12-Channel DS3/STS-1 to STS-12 Mapper IC. Continuing on with this line of thought, if a Mapper IC is configured to receive an STS-N signal, and (from this STS-N signal) de-map and output N DS3 signals (towards the DS3 facility), then it will typically do so in the following manner.
* In many cases, the Mapper IC will output this DS3 signal, using both a "Data-Signal" and a "Clock-Signal".
In many cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data-Signal.
* However, as the Mapper IC output this STS-1 data-stream, it will typically supply clock pulses (via the ClockSignal output) coincident to whenever a DS3 bit is being output via the Data-Signal. In this case, the Mapper IC will NOT supply a clock pulse coincident to when a TOH, POH, or any "non-DS3 data-bit" is being output via the "Data-Signal". Now, since the Mapper IC will output the entire STS-1 data stream (via the Data-Signal), the output ClockSignal will be of the form such that it has a period of 19.3ns (e.g., a 51.84MHz clock signal). However, the Mapper IC will still generate approximately 44,736,000 clock pulses during any given one second period. Hence, the clock signal that is output from the Mapper IC will be a horribly gapped 44.736MHz clock signal. One can view such a clock signal as being a very-jittery 44.736MHz clock signal. This jitter that exists within the "Clock-Signal" is referred to as "Clock-Gapping" Jitter. A more detailed discussion on how the user must handle this type of jitter is presented in "Section 7.8.2, Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU" on page 88.
7.5 A Review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications
The "Category I Intrinsic Jitter Requirements" per Telcordia GR-253-CORE (for DS3 applications) mandates that the user perform a large series of tests against certain specified "Scenarios". These "Scenarios" and their corresponding requirements is summarized in Table 19, below.
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
APPLICATIONS
SCENARIO DESCRIPTION DS3 De-Mapping Jitter Single Pointer Adjustment
SCENARIO NUMBER
TELCORDIA GR-253-CORE CATEGORY I INTRINSIC JITTER REQUIREMENTS 0.4UI-pp
COMMENTS
Includes effects of De-Mapping and Clock Gapping Jitter Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments.NOTE: Ao is the amount of intrinsic jitter that was measured during the "DS3 DeMapping Jitter" phase of the Test. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments.
A1
0.3UI-pp + Ao
Pointer Bursts Phase Transients 87-3 Pattern 87-3 Add 87-3 Cancel Continuous Pattern
A2 A3 A4 A5 A5 A4
1.3UI-pp 1.2UI-pp 1.0UI-pp 1.3UI-pp 1.3UI-pp 1.0UI-pp
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APPLICATIONS
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
TELCORDIA GR-253-CORE CATEGORY I INTRINSIC JITTER REQUIREMENTS 1.3UI-pp 1.3UI-pp
SCENARIO DESCRIPTION Continuous Add Continuous Cancel
SCENARIO NUMBER A5 A5
COMMENTS
Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments. Includes effects of Jitter from Clock-Gapping, De-Mapping and Pointer Adjustments.
NOTE: All of these intrinsic jitter measurements are to be performed using a band-pass filter of 10Hz to 400kHz.
Each of the scenarios presented in Table 19, are briefly described below.
7.5.1 DS3 De-Mapping Jitter
DS3 De-Mapping Jitter is the amount of Intrinsic Jitter that will be measured within the "Line" or "Facility-side" DS3 signal, (after it has been de-mapped from a SONET signal) without the occurrence of "Pointer Adjustments" within the SONET signal. Telcordia GR-253-CORE requires that the "DS3 De-Mapping" Jitter be less than 0.4UI-pp, when measured over all possible combinations of DS3 and STS-1 frequency offsets.
7.5.2 Single Pointer Adjustment
Telcordia GR-253-CORE states that if each pointer adjustment (within a continuous stream of pointer adjustments) is separated from each other by a period of 30 seconds, or more; then they are sufficiently isolated to be considered "Single-Pointer Adjustments". Figure 56 presents an illustration of the "Single Pointer Adjustment" Scenario.
FIGURE 56. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO
Pointer Adjustment Events
>30s
Initialization
Cool Down
Measurement Period
Telcordia GR-253-CORE states that the Intrinsic Jitter that is measured (within the DS3 signal) that is ultimately de-mapped from a SONET signal that is experiencing "Single-Pointer Adjustment" events, must NOT exceed the value 0.3UI-pp + Ao.
NOTES: 1. 2. Ao is the amount of Intrinsic Jitter that was measured during the "De-Mapping" Jitter portion of this test. Testing must be performed for both Incrementing and Decrementing Pointer Adjustments.
7.5.3
Pointer Burst
Figure 57 presents an illustration of the "Pointer Burst" Pointer Adjustment Scenario per Telcordia GR-253CORE.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FIGURE 57. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO
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Pointer Adjustment Events
Pointer Adjustment Burst Train
t
0.5ms 0.5ms
>30s
Initialization
Cool Down
Measurement Period
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Burst of Pointer Adjustment" scenario, must NOT exceed 1.3UI-pp.
7.5.4 Phase Transients
Figure 58 presents an illustration of the "Phase Transients" Pointer Adjustment Scenario per Telcordia GR253-CORE.
FIGURE 58. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO
Pointer Adjustment Events
Pointer Adjustment Burst Train
0.5s
0.25s
0.25s
t
>30s
Initialization
Cool Down
Measurement Period
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Phase Transient - Pointer Adjustment" scenario must NOT exceed 1.2UI-pp.
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7.5.5
87-3 Pattern
Figure 59 presents an illustration of the "87-3 Continuous Pattern" Pointer Adjustment Scenario per Telcordia GR-253-CORE.
FIGURE 59. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN
Repeating 87-3 Pattern (see below)
Pointer Adjustment Events
Initialization
Measurement Period
87-3 Pattern
87 Pointer Adjustment Events
No Pointer Adjustments
T
NOTE: T ranges from 34ms to 10s (Req) T ranges from 7.5ms to 34ms (Obj)
Telcordia GR-253-CORE defines an "87-3 Continuous" Pointer Adjustment pattern, as a repeating sequence of 90 pointer adjustment events. Within this 90 pointer adjustment event, 87 pointer adjustments are actually executed. The remaining 3 pointer adjustments are never executed. The spacing between individual pointer adjustment events (within this scenario) can range from 7.5ms to 10seconds. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "87-3 Continuous" pattern of Pointer Adjustments, must not exceed 1.0UI-pp.
7.5.6 87-3 Add
Figure 60 presents an illustration of the "87-3 Add Pattern" Pointer Adjustment Scenario per Telcordia GR-253CORE.
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Added Pointer Adjustment No Pointer Adjustments 43 Pointer Adjustments 43 Pointer Adjustments
T
t
Telcordia GR-253-CORE defines an "87-3 Add" Pointer Adjustment, as the "87-3 Continuous" Pointer Adjustment pattern, with an additional pointer adjustment inserted, as shown above in Figure 60. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "87-3 Add" pattern of Pointer Adjustments, must not exceed 1.3UIpp.
7.5.7 87-3 Cancel
Figure 61 presents an illustration of the 87-3 Cancel Pattern Pointer Adjustment Scenario per Telcordia GR253-CORE.
FIGURE 61. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO
86 or 87 Pointer Adjustments
No Pointer Adjustments
T
Cancelled Pointer Adjustment
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Telcordia GR-253-CORE defines an "87-3 Cancel" Pointer Adjustment, as the "87-3 Continuous" Pointer Adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in Figure 61. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "87-3 Cancel" pattern of Pointer Adjustments, must not exceed 1.3UIpp.
7.5.8 Continuous Pattern
Figure 62 presents an illustration of the "Continuous" Pointer Adjustment Scenario per Telcordia GR-253CORE.
FIGURE 62. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO
Repeating Continuous Pattern (see below)
Pointer Adjustment Events
Initialization
Measurement Period T
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Continuous" pattern of Pointer Adjustments, must not exceed 1.0UIpp. The spacing between individual pointer adjustments (within this scenario) can range from 7.5ms to 10s.
7.5.9 Continuous Add
Figure 63 presents an illustration of the "Continuous Add Pattern" Pointer Adjustment Scenario per Telcordia GR-253-CORE.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER FIGURE 63. ILLUSTRATION OF CONTINUOUS-ADD POINTER ADJUSTMENT SCENARIO
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Added Pointer Adjustment
Continuous Pointer Adjustments
Continuous Pointer Adjustments
T
t
Telcordia GR-253-CORE defines an "Continuous Add" Pointer Adjustment, as the "Continuous" Pointer Adjustment pattern, with an additional pointer adjustment inserted, as shown above in Figure 63. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Continuous Add" pattern of Pointer Adjustments, must not exceed 1.3UI-pp.
7.5.10 Continuous Cancel
Figure 64 presents an illustration of the "Continuous Cancel Pattern" Pointer Adjustment Scenario per Telcordia GR-253-CORE.
FIGURE 64. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO
Continuous Pointer Adjustments
T
Cancelled Pointer Adjustment
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Telcordia GR-253-CORE defines a "Continuous Cancel" Pointer Adjustment, as the "Continuous" Pointer Adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in Figure 64. Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a SONET signal, which is experiencing the "Continuous Cancel" pattern of Pointer Adjustments, must not exceed 1.3UI-pp.
7.6 7.7 A Review of the DS3 Wander Requirements per ANSI T1.105.03b-1997. A Review of the Intrinsic Jitter and Wander Capabilities of the LIU in a typical system application Intrinsic Jitter Test results
To be provided in the next revision of this data sheet.
The Intrinsic Jitter and Wander Test results are summarized in this section.
7.7.1
The Intrinsic Jitter Test results for the LIU in DS3 being de-mapped from SONET is summarized below in Table 2.
TABLE 20: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS
SCENARIO DESCRIPTION DS3 De-Mapping Jitter Single Pointer Adjustment Pointer Bursts Phase Transients 87-3 Pattern 87-3 Add 87-3 Cancel Continuous Pattern Continuous Add Continuous Cancel NOTES: A1 SCENARIO NUMBER LIU INTRINSIC JITTER TEST RESULTS 0.13UI-pp TELCORDIA GR-253-CORE CATEGORY I INTRINSIC JITTER REQUIREMENTS 0.4UI-pp
0.201UI-pp
0.43UI-pp (e.g. 0.13UI-pp + 0.3UI-pp)
A2 A3 A4 A5 A5 A4
0.582UI-pp 0.526UI-pp 0.790UI-pp 0.926UI-pp 0.885UI-pp 0.497UI-pp
1.3UI-pp 1.2UI-pp 1.0UI-pp 1.3UI-pp 1.3UI-pp 1.0UI-pp
A5 A5
0.598UI-pp 0.589UI-pp
1.3UI-pp 1.3UI-pp
1. 2. 3.
A detailed test report on our Test Procedures and Test Results is available and can be obtained by contacting your Exar Sales Representative. These test results were obtained via the LIUs mounted on our XRT94L43 12-Channel DS3/E3/STS-1 Mapper Evaluation Board. These same results apply to SDH/AU-3 Mapping applications.
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Wander Measurement test results will be provided in the next revision of the LIU Data Sheet. In this section, we will discuss the following topics.
* How to design with and configure the LIU to permit a system to meet the above-mentioned Intrinsic Jitter and
Wander requirements.
* How is the LIU able to meet the above-mentioned requirements? * How does the LIU permits the user to comply with the SONET APS Recovery Time requirements of 50ms
(per Telcordia GR-253-CORE)?
* How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end Customer's site?
7.8.1 How to design and configure the LIU to permit a system to meet the above-mentioned Intrinsic Jitter and Wander requirements
As mentioned earlier, in most application (in which the LIU will be used in a SONET De-Sync Application) the user will typically interface the LIU to a Mapper device in the manner as presented below in Figure 65. In this application, the Mapper has the responsibility of receiving a SONET STS-N/OC-N signal and extracting as many as N DS3 signals from this signal. As a given channel within the Mapper IC extracts out a given DS3 signal (from SONET) it will typically be applying a Clock and Data signal to the "Transmit Input" of the LIU IC. Figure 65 presents a simple illustration as to how one channel, within the LIU should be connected to the Mapper IC.
FIGURE 65. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS
De-Mapped (Gapped) DS3 Data and Clock
TPDATA_n input pin
STS-N Signal
DS3 to STS-N DS3 to STS-N Mapper/ Mapper/ Demapper Demapper IC IC
LIU LIU
TCLK n input
As mentioned above, the Mapper IC will typically output a Clock and Data signal to the LIU. In many cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data Signal to the LIU. However, the Mapper IC typically only supplies a clock pulse via the Clock Signal to the LIU coincident to whenever a DS3 bit is being output via the Data Signal. In this case, the Mapper IC would not supply a clock edge coincident to when a TOH, POH or any non-DS3 data-bit is being output via the Data-Signal. Figure 65 indicates that the Data Signal from the Mapper device should be connected to the TPDATA_n input pin of the LIU IC and that the Clock Signal from the Mapper device should be connected to the TCLK_n input pin of the LIU IC. In this application, the LIU has the following responsibilities.
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* Using a particular clock edge within the "gapped" clock signal (from the Mapper IC) to sample and latch the
value of each DS3 data-bit that is output from the Mapper IC.
* To (through the user of the Jitter Attenuator block) attenuate the jitter within this "DS3 data" and "clock signal"
that is output from the Mapper IC.
* To convert this "smoothed" DS3 data and clock into industry-compliant DS3 pulses, and to output these
pulses onto the line. To configure the LIU to operate in the correct mode for this application, the user must execute the following configuration steps.
a. Configure the LIU to operate in the DS3 Mode
The user can configure a given channel (within the LIU) to operate in the DS3 Mode, by executing either of the following steps.
* If the LIU has been configured to operate in the Host Mode
The user can accomplish this by setting both Bits 2 (E3_n) and Bits 1 (STS-1/DS3*_n), within each of the "Channel Control Registers" to "0" as depicted below.
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 CHANNEL 1 ADDRESS LOCATION = 0X0E CHANNEL 2 ADDRESS LOCATION = 0X16
BIT 7 Unused R/O 0 R/O 0 BIT 6 BIT 5 PRBS Enable Ch_n R/W 0 BIT 4 RLB_n R/W 0 BIT 3 LLB_n R/W 0 BIT 2 E3_n R/W 0 BIT 1 STS-1/DS3_n R/W 0 BIT 0 SR/DR_n R/W 0
* If the LIU has been configured to operate in the Hardware Mode
The user can accomplish this by pulling all of the following input pins "Low". Pin 76 - E3_0 Pin 94 - E3_1 Pin 85 - E3_2 Pin 72 - STS-1/DS3_0 Pin 98 - STS-1/DS3_1 Pin 81 - STS-1/DS3_2
b. Configure the LIU to operate in the Single-Rail Mode
Since the Mapper IC will typically output a single "Data Line" and a "Clock Line" for each DS3 signal that it demaps from the incoming STS-N signal, it is imperative to configure each channel within the LIU to operate in the Single Rail Mode. The user can accomplish this by executing either of the following steps.
* If the LIU has been configured to operate in the Host Mode
The user can accomplish this by setting Bit 0 (SR/DR*), within the each of the "Channel Control" Registers to 1, as illustrated below.
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 CHANNEL 1 ADDRESS LOCATION = 0X0E CHANNEL 2 ADDRESS LOCATION = 0X16
BIT 7 Unused BIT 6 BIT 5 PRBS Enable Ch_n R/O 0 R/W 0 BIT 4 RLB_n BIT 3 LLB_n BIT 2 E3_n BIT 1 STS-1/
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BIT 0 SR/DR_n
DS3_n
R/W 0 R/W 0 R/W 0 R/W 0 R/W 1
R/O 0
* If the LIU has been configured to operate in the Hardware Mode
Then the user should tie pin 65 (SR/DR*) to "High".
c. Configure each of the channels within the LIU to operate in the SONET De-Sync Mode
The user can accomplish this by executing either of the following steps.
* If the LIU has been configured to operate in the Host Mode.
Then the user should set Bit D2 (JA1) to "0" and Bit D0 (JA0) to "1", within the Jitter Attenuator Control Register, as depicted below.
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time DisableCh_n R/O 0 R/W 0 BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
R/O 0
R/O 0
R/W 0
R/W 0
R/W 0
R/W 1
* If the LIU has been configured to operate in the Hardware Mode
Then the user should tie pin 44 (JA0) to a logic "HIGH" and pin 42 (JA1) to a logic "LOW". Once the user accomplishes either of these steps, then the Jitter Attenuator (within the LIU) will be configured to operate with a very narrow bandwidth.
d. Configure the Jitter Attenuator (within each of the channels) to operate in the Transmit Direction.
The user can accomplish this by executing either the following steps.
* If the LIU has been configured to operate in the Host Mode.
Then the user should be Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted below.
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JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time DisableCh_n R/O 0 R/W 0 BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
R/O 0
R/O 0
R/W 0
R/W 0
R/W 1
R/W 1
* If the LIU has been configured to operate in the Hardware Mode.
Then the user should tie pin 43 (JATx/JARx*) to "1".
e. Enable the "SONET APS Recovery Time" Mode
Finally, if the user intends to use the LIU in an Application that is required to reacquire proper SONET and DS3 traffic, prior within 50ms of an APS (Automatic Protection Switching) event (per Telcordia GR-253-CORE), then the user should set Bit 4 (SONET APS Recovery Time Disable), within the "Jitter Attenuator Control" Register, to "0" as depicted below.
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time DisableCh_n R/O 0 R/W 0 BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
R/O 0 NOTES: 1.
R/O 0
R/W 0
R/W 0
R/W 0
R/W 1
The ability to disable the "SONET APS Recovery Time" mode is only available if the LIU is operating in the Host Mode. If the LIU is operating in the "Hardware" Mode, then this "SONET APS Recovery Time Mode" feature will always be enabled. The "SONET APS Recovery Time" mode will be discussed in greater detail in "Section 7.8.3, How does the LIU permit the user to comply with the SONET APS Recovery Time requirements of 50ms (per Telcordia GR-253CORE)?" on page 92.
2.
7.8.2
Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU
In order to minimize the effects of "Clock-Gapping" Jitter within the DS3 signal that is ultimately transmitted to the DS3 Line (or facility), we recommend that some "pre-processing" of the "Data-Signals" and "Clock-Signals" (which are output from the Mapper device) be implemented prior to routing these signals to the "Transmit Inputs" of the LIU.
7.8.2.1 SOME NOTES PRIOR TO STARTING THIS DISCUSSION:
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Our simulation results indicate that Jitter Attenuator PLL (within the LIU LIU IC) will have no problem handling and processing the "Data-Signal" and "Clock-Signal" from a Mapper IC/ASIC if no pre-processing has been performed on these signals. In order words, our simulation results indicate that the Jitter Attenuator PLL (within the LIU IC) will have no problem handling the "worst-case" of 59 consecutive bits of no clock pulses in the "Clock-Signal (due to the Mapper IC processing the TOH bytes, an Incrementing Pointer-Adjustmentinduced "stuffed-byte", the POH byte, and the two fixed-stuff bytes within the STS-1 SPE, etc), immediately followed be processing clusters of DS3 data-bits (as shown in Figure 45) and still comply with the "Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE for DS3 applications.
NOTE: If this sort of "pre-processing" is already supported by the Mapper device that you are using, then no further action is required by the user.
7.8.2.2
OUR PRE-PROCESSING RECOMMENDATIONS
For the time-being, we recommend that the customer implement the "pre-processing" of the DS3 "Data-Signal" and "Clock-Signal" as described below. Currently we are aware that some of the Mapper products on the Market do implement this exact "pre-processing" algorithm. However, if the customer is implementing their Mapper Design in an ASIC or FPGA solution, then we strongly recommend that the user implement the necessary logic design to realize the following recommendations. Some time ago, we spent some time, studying (and then later testing our solution with) the PM5342 OC-3 to DS3 Mapper IC from PMC-Sierra. In particular, we wanted to understand the type of "DS3 Clock" and "Data" signal that this DS3 to OC-3 Mapper IC outputs. During this effort, we learned the following.
1. This "DS3 Clock" and "Data" signal, which is output from the Mapper IC consists of two major "repeating" patterns (which we will refer to as "MAJOR PATTERN A" and "MAJOR PATTERN B". The behavior of each of these patterns is presented below. MAJOR PATTERN A
MAJOR PATTERN A consists of two "sub" or minor-patterns, (which we will refer to as "MINOR PATTERN P1 and P2). MINOR PATTERN P1 consists of a string of seven (7) clock pulses, followed by a single gap (no clock pulse). An illustration of MINOR PATTERN P1 is presented below in Figure 66.
FIGURE 66. ILLUSTRATION OF MINOR PATTERN P1
Missing Clock Pulse
1
2
3
4
5
6
7
It should be noted that each of these clock pulses has a period of approximately 19.3ns (or has an "instantaneously frequency of 51.84MHz). MINOR Pattern P2 consists of string of five (5) clock pulses, which is also followed by a single gap (no clock pulse). An illustration of Pattern P2 is presented below in Figure 67.
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FIGURE 67. ILLUSTRATION OF MINOR PATTERN P2
Missing Clock Pulse
1
2
3
4
5
HOW MAJOR PATTERN A IS SYNTHESIZED
MAJOR PATTERN A is created (by the Mapper IC) by:
* Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times. * Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times. Figure 68 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN A
FIGURE 68. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A
Repeats 63 Times MINOR PATTERN P1
Repeats 36 Times MINOR PATTERN P2
Hence, MAJOR PATTERN A consists of "(63 x 7) + (36 x 5)" = 621 clock pulses. These 621 clock pulses were delivered over a period of "(63 x 8) + (36 x 6)" = 720 STS-1 (or 51.84MHz) clock periods.
MAJOR PATTERN B
MAJOR PATTERN B consists of three sub or minor-patterns (which we will refer to as "MINOR PATTERNS P1, P2 and P3). MINOR PATTERN P1, which is used to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR PATTERN P1" as was presented above in Figure 38. Similarly, the MINOR PATTERN P2, which is also used to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR PATTERN P2" as was presented in Figure 39. MINOR PATTERN P3 (which has yet to be defined) consists of a string of six (6) clock pulses, which contains no gaps. An illustration of MINOR PATTERN P3 is presented below in Figure 69.
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1
2
3
4
5
6
HOW MAJOR PATTERN B IS SYNTHESIZED
MAJOR PATTERN B is created (by the Mapper IC) by:
* Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times. * Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times.
* pon completion of the 35th transmission of MINOR PATTERN P2, MINOR PATTERN P3 is transmitted once.
Figure 70 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN B.
FIGURE 70. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B
Transmitted 1 Time Repeats 63 Times PATTERN P1 Repeats 35 Times PATTERN P2 PATTERN P3
Hence, MAJOR PATTERN B consists of "(63 x 7) + (35 x 5)" + 6 = 622 clock pulses. These 622 clock pulses were delivered over a period of "(63 x 8) + (35 x 6) + 6 = 720 STS-1 (or 51.84MHz) clock periods.
PUTTING THE PATTERNS TOGETHER
Finally, the DS3 to OC-N Mapper IC clock output is reproduced by doing the following.
* MAJOR PATTERN A is transmitted two times (repeatedly). * After the second transmission of MAJOR PATTERN A, MAJOR PATTERN B is transmitted once. * Then the whole process repeats.
Throughout the remainder of this document, we will refer to this particular pattern as the "SUPER PATTERN". Figure 71 presents an illustration of this "SUPER PATTERN" which is output via the Mapper IC.
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FIGURE 71. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC
PATTERN A
PATTERN A
PATTERN B
CROSS-CHECKING OUR DATA
* Each SUPER PATTERN consists of (621 + 621 + 622) = 1864 clock pulses. * The total amount of time, which is required for the "DS3 to OC-N Mapper" IC to transmit this SUPER
PATTERN is (720 + 720 + 720) = 2160 "STS-1" clock periods.
* This amount to a period of (2160/51.84MHz) = 41,667ns. * In a period of 41, 667ns, the LIU (when configured to operate in the DS3 Mode), will output a total (41,667ns
x 44,736,000) = 1864 uniformly spaced DS3 clock pulses.
* Hence, the number of clock pulses match.
APPLYING THE SUPER PATTERN TO THE LIU
Whenever the LIU is configured to operate in a "SONET De-Sync" application, the device will accept a continuous string of the above-defined SUPER PATTERN, via the TCLK input pin (along with the corresponding data). The channel within the LIU (which will be configured to operate in the "DS3" Mode) will output a DS3 line signal (to the DS3 facility) that complies with the "Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 applications). This scheme is illustrated below in Figure 72.
FIGURE 72. SIMPLE ILLUSTRATION OF THE LIU BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION
De-Mapped (Gapped) DS3 Data and Clock
TPDATA_n input pin
STS-N Signal
DS3 to STS-N DS3 to STS-N Mapper/ Mapper/ Demapper Demapper IC IC
LIU LIU
TCLK_n input
7.8.3
How does the LIU permit the user to comply with the SONET APS Recovery Time requirements of 50ms (per Telcordia GR-253-CORE)?
Telcordia GR-253-CORE, Section 5.3.3.3 mandates that the "APS Completion" (or Recovery) time be 50ms or less. Many of our customers interpret this particular requirement as follows. "From the instant that an APS is initiated on a high-speed SONET signal, all lower-speed SONET traffic (which is being transported via this "high-speed" SONET signal) must be fully restored within 50ms. Similarly, if the "high-speed" SONET signal is transporting some PDH signals (such as DS1 or DS3, etc.), then those entities
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that are responsible for acquiring and maintaining DS1 or DS3 frame synchronization (with these DS1 or DS3 data-streams that have been de-mapped from SONET) must have re-acquired DS1 or DS3 frame synchronization within 50ms" after APS has been initiated." The LIU was designed such that the DS3 signals that it receives from a SONET Mapper device and processes will comply with the Category I Intrinsic Jitter requirements per Telcordia GR-253-CORE. Reference 1 documents some APS Recovery Time testing, which was performed to verify that the Jitter Attenuator blocks (within the LIU) device that permit it to comply with the Category I Intrinsic Jitter Requirements (for DS3 Applications) per Telcordia GR-253-CORE, do not cause it to fail to comply with the "APS Completion Time" requirements per Section 5.3.3.3 of Telcordia GR-253-CORE. However, Table 3 presents a summary of some APS Recovery Time requirements that were documented within this test report. Table 3,
TABLE 21: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET
DS3 PPM OFFSET (PER W&G ANT-20SE) -99 ppm -40ppm -30 ppm -20 ppm -10 ppm 0 ppm +10 ppm +20 ppm +30 ppm +40 ppm +99 ppm NOTE: The APS Completion (or Recovery) time requirement is 50ms. MEASURED APS RECOVERY TIME (PER LOGIC ANALYZER) 1.25ms 1.54ms 1.34ms 1.49ms 1.30ms 1.89ms 1.21ms 1.64ms 1.32ms 1.25ms 1.35ms
Configuring the LIU to be able to comply with the SONET APS Recovery Time Requirements of 50ms
Quite simply, the user can configure a given Jitter Attenuator block (associated with a given channel) to (1) comply with the "APS Completion Time" requirements per Telcordia GR-253-CORE, and (2) also comply with the "Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 applications) by making sure that Bit 4 (SONET APS Recovery Time Disable Ch_n), within the Jitter Attenuator Control Register is set to "0" as depicted below.
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time Disable Ch_n BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 R/O 0 BIT 6 R/O 0 BIT 5 R/O 0 BIT 4 R/W 0 BIT 3 R/W 0 BIT 2 R/W 0 BIT 1 R/W 1 BIT 0 R/W 1
NOTE: The user can only disable the "SONET APS Recovery Time Mode" if the LIU is operating in the Host Mode. If the user is operating the LIU in the Hardware Mode, then the user will have NO ability to disable the "SONET APS Recovery Time Mode" feature.
7.8.4
How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end Customer's site?
Daisy-Chain testing is emerging as a new requirements that many of our customers are imposing on our SONET Mapper and LIU products. Many System Designer/Manufacturers are finding out that whenever their end-customers that are evaluating and testing out their systems (in order to determine if they wish to move forward and start purchasing this equipment in volume) are routinely demanding that they be able to test out these systems with a single piece of test equipment. This means that the end-customer would like to take a single piece of DS3 or STS-1 test equipment and (with this test equipment) snake the DS3 or STS-1 traffic (that this test equipment will generate) through many or (preferably all) channels within the system. For example, we have had request from our customers that (on a system that supports OC-192) our silicon be able to support this DS3 or STS-1 traffic snaking through the 192 DS3 or STS-1 ports within this system. After extensive testing, we have determined that the best approach to complying with test "Daisy-Chain" Testing requirements, is to configure the Jitter Attenuator blocks (within each of the Channels within the LIU) into the "32-Bit" Mode. The user can configure the Jitter Attenuator block (within a given channel of the LIU) to operate in this mode by settings in the table below.
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 CHANNEL 1 ADDRESS LOCATION = 0X0F CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7 BIT 6 Unused BIT 5 BIT 4 SONET APS Recovery Time Disable Ch_n R/O 0 R/W 0 BIT 3 JA RESET Ch_n BIT 2 JA1 Ch_n BIT 1 JA in Tx Path Ch_n BIT 0 JA0 Ch_n
R/O 0
R/O 0
R/W 0
R/W 1
R/W 1
R/W 0
REFERENCES
1. TEST REPORT - AUTOMATIC PROTECTION SWITCHING (APS) RECOVERY TIME TESTING WITH THE XRT94L43 DS3/E3/STS-1 TO STS-12 MAPPER IC - Revision C Silicon
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
8.0 ELECTRICAL CHARACTERISTICS TABLE 22: ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER Supply Voltage Input Voltage at any Pin Input current at any pin Storage Temperature Ambient Operating Temperature Thermal Resistance
MIN
MAX
UNITS
COMMENTS
VDD VIN IIN STEMP ATEMP Theta JA
-0.5 -0.5
6.0 5.5 100
V V mA
0C 0C 0
Note 1 Note 1 Note 1 Note 1 linear airflow 0 ft./min linear air flow 0ft/min (See Note 3 below)
-65 -40
150 85 23
C/W
MLEVL
Exposure to Moisture
4
level
EIA/JEDEC JESD22-A112-A
ESD NOTES: 1. 2. 3.
ESD Rating
2000
V
Note 2
Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair reliability of the device. ESD testing method is per MIL-STD-883D,M-3015.7 With Linear Air flow of 200 ft/min, reduce Theta JA by 20%, Theta JC is unchanged.
TABLE 23: DC ELECTRICAL CHARACTERISTICS:
SYMBOL
PARAMETER Digital Supply Voltage Analog Supply Voltage Supply current requirements Power Dissipation Input Low Voltage Input High Voltage Output Low Voltage, IOUT = - 4mA Output High Voltage, IOUT = 4 mA Input Leakage Current1 Input Capacitance Load Capacitance
MIN.
TYP.
MAX.
UNITS
DVDD AVDD ICC PDD VIL VIH VOL VOH IL CI CL NOTES: 1. 2.
3.135 3.135
3.3 3.3 TBD TBD
3.465 3.465 TBD TBD 0.8
V V mA W V V V V
2.0
5.5 0.4
2.4 10 10 10
A pF pF
Not applicable for pins with pull-up or pull-down resistors. The Digital inputs are TTL 5V compliant.
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APPENDIX A
TABLE 24: TRANSFORMER RECOMMENDATIONS
PARAMETER VALUE
Turns Ratio Primary Inductance Isolation Voltage Leakage Inductance
1:1 40 H 1500 Vrms 0.6 H
TABLE 25: TRANSFORMER DETAILS
PART NUMBER VENDOR INSULATION PACKAGE TYPE
PE-68629 PE-65966 PE-65967 T 3001 TG01-0406NS TTI 7601-SM
PULSE PULSE PULSE PULSE HALO TransPower
3000 V 1500 V 1500 V 1500 V 1500 V 1500 V
Large Thru-hole Small Thru-hole SMT SMT SMT SMT
TRANSFORMER VENDOR INFORMATION Pulse Corporate Office 12220 World Trade Drive San Diego, CA 92128 Tel: (858)-674-8100 FAX: (858)-674-8262 Europe 1 & 2 Huxley Road The Surrey Research Park Guildford, Surrey GU2 5RE United Kingdom Tel: 44-1483-401700 FAX: 44-1483-401701
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
Asia 150 Kampong Ampat #07-01/02 KA Centre Singapore 368324 Tel: 65-287-8998 Website: http://www.pulseeng.com Halo Electronics Corporate Office P.O. Box 5826 Redwood City, CA 94063 Tel: (650)568-5800 FAX: (650)568-6165 Email: info@haloelectronics.com Website: http://www.haloelectronics.com Transpower Technologies, Inc. Corporate Office Park Center West Building 9805 Double R Blvd, Suite # 100 Reno, NV 89511 (800)500-5930 or (775)852-0140 Email: info@trans-power.com Website: http://www.trans-power.com
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ORDERING INFORMATION
PART NUMBER XRT75L06DIB PACKAGE 217 Lead BGA (23 x 23 mm) OPERATING TEMPERATURE RANGE - 40C to + 85C
PACKAGE DIMENSIONS - 23 X 23 MM 217 LEAD BGA PACKAGE
BOTTOM VIEW (A1 corner feature is mfger option)
Note: The control dimension is in millimeter. INCHES MIN MAX 0.067 0.098 0.016 0.028 0.012 0.024 0.039 0.047 0.898 0.913 0.800 BSC 0.780 0.795 0.024 0.035 0.050 BSC 10 20 MILLIMETERS MIN MAX 1.70 2.50 0.40 0.70 0.30 0.60 1.00 1.20 22.80 23.20 20.32 BSC 19.80 20.20 0.60 0.90 1.27 BSC 10 20
SYMBOL A A1 A2 A3 D D1 D2 b e
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XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REVISIONS
REVISION P1.0.0 P1.0.2 DATE Original COMMENTS
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Renamed the pins DJA and FSS. Included the Clock out and Clock enable function for the Single Frequency Mode. Changed the TxON pin from internal pull down to pull up.Changed the operation of TxON in Host Mode.Included internal monitoring feature. LOSMUT bit operation description was changed.
06/03 10/30 03/04 04/05
P1.0.3 P1.0.4 1.0.1 1.0.2 1.0.3 1.0.4
Removed the TQFP package information since no longer offered in TQFP. Re-arranged the datasheet and finalized the electrical specifications. Changed the Device ID to reflect the correct value. Edited the Moisture Level. Fix SONET de-sync mode in JA register and description1.0.4.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet April 2005. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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